PCF8578H/1,118 NXP Semiconductors, PCF8578H/1,118 Datasheet - Page 18

IC LCD DRIVER DOT MATRIX 64-LQFP

PCF8578H/1,118

Manufacturer Part Number
PCF8578H/1,118
Description
IC LCD DRIVER DOT MATRIX 64-LQFP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCF8578H/1,118

Display Type
LCD
Configuration
Dot Matrix
Interface
I²C
Voltage - Supply
2.5 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Digits Or Characters
-
Lead Free Status / Rohs Status
 Details
Other names
935276284118
PCF8578H/1-T
PCF8578H/1-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCF8578H/1,118
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
PCF8578_6
Product data sheet
Fig 13. System configuration
SDA
SCL
8.8.4 Acknowledge
TRANSMITTER /
RECEIVER
MASTER
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after the reception of each byte. Also
a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges must pull down the
SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be
taken into consideration). A master receiver must signal the end of a data transmission to
the transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
Fig 11. Bit transfer
Fig 12. Definition of START and STOP condition
SDA
SCL
RECEIVER
SLAVE
START condition
SDA
SCL
S
Rev. 06 — 5 May 2009
TRANSMITTER /
LCD row/column driver for dot matrix graphic displays
RECEIVER
SLAVE
data valid
data line
stable;
change
allowed
of data
TRANSMITTER
MASTER
STOP condition
TRANSMITTER /
mba607
RECEIVER
MASTER
P
PCF8578
© NXP B.V. 2009. All rights reserved.
mba605
mba608
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