SI3402-A-GM Silicon Laboratories Inc, SI3402-A-GM Datasheet - Page 16

IC POE PD LOW EMI SW REG 20VQFN

SI3402-A-GM

Manufacturer Part Number
SI3402-A-GM
Description
IC POE PD LOW EMI SW REG 20VQFN
Manufacturer
Silicon Laboratories Inc
Type
Power over Ethernet Switch (PoE)r
Datasheet

Specifications of SI3402-A-GM

Package / Case
20-VQFN
Applications
IP Phones, Power over LAN, Network Routers and Switches
Internal Switch(s)
Yes
Current Limit
470mA
Voltage - Supply
2.8 V ~ 57 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Product
PoE / LAN Solutions
Supply Voltage (max)
57 V
Supply Voltage (min)
2.8 V
Power Dissipation
1.2 W
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Si3402
4. Pin Descriptions
16
9, Pad
Pin#
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
ISOSSFT
EROUT
VPOSS
PLOSS
VPOSF
Name
VNEG
RDET
VSSA
SSFT
VSS1
VSS2
SWO
VDD
HSO
RCL
SP2
SP1
CT2
CT1
FB
Error-amplifier output and PWM input; directly connected to opto-coupler in isolated application.
Soft-start output pin ramps voltage across external soft-start capacitor to allow switcher to ramp
output slowly.
5 V supply rail for switcher; provides drive for opto-coupler.
0.1 µF capacitor between this pin and VSSA for isolated applications.
Early power loss indicator; open drain output is pulled to VPOS when VPORT is applied.
Input pin for external precision detection resistor; also used for establishing absolute current
reference.
Hotswap switch output; connects to VNEG through hotswap switch.
Input pin for external precision classification resistor; float if optional RCLASS is unused.
Rectified high-voltage supply, negative rail. Must be connected to thermal PAD node (VNEG)
on package bottom. This thermal pad must be connected to VNEG (pin #9) as well as a 2 in
heat spreader plane using a minimum of nine thermal vias.
High-voltage supply input from spare pair; polarity-insensitive.
High-voltage supply input from spare pair; polarity-insensitive.
Rectified high-voltage supply, positive rail (force node)
High-voltage supply input from center tap of Ethernet transformer; polarity-insensitive.
High-voltage supply input from center tap of Ethernet transformer; polarity-insensitive.
Analog ground.
Rectified high-voltage supply, positive rail sense node.
Negative supply rail for switcher; externally tied to HSO.
Switching transistor output; drain of switching N-FET.
Negative supply rail for switcher; externally tied to HSO.
Regulated feedback input in non-isolated application.
Isolated mode soft start enable input. Tie to VDD for non-isolated applications. Connect a
Table 12. Si3402 Pin Descriptions (Top View)
ISOSSFT
EROUT
SSFT
VDD
1
2
3
4
20
5
19
6
Rev. 1.1
18
VNEG
(PAD)
7
17
8
16
9
Description
10
15
14
13
12
11
CT2
CT1
VPOSF
SP1
2

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