SI3402-A-GM Silicon Laboratories Inc, SI3402-A-GM Datasheet - Page 8

• Manufacturer Part Number: SI3402-A-GM
• Description: IC POE PD LOW EMI SW REG 20VQFN
• Manufacturer: Silicon Laboratories Inc
• Type: Power over Ethernet Switch (PoE)r

Specifications of SI3402-A-GM

• Package / Case: 20-VQFN
• Applications: IP Phones, Power over LAN, Network Routers and Switches
• Internal Switch(s): Yes
• Current Limit: 470mA
• Voltage - Supply: 2.8 V ~ 57 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: PoE / LAN Solutions
• Supply Voltage (max): 57 V
• Supply Voltage (min): 2.8 V
• Power Dissipation: 1.2 W
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si3402
Table 5. Electrical Characteristics (Continued)
Table 6. Total Power Dissipation
Table 7. Package Thermal Characteristics
8
Description
*Note: Silicon Laboratories recommends the on-chip diode bridges be bypassed when output power requirements are >10 W
Parameter
Parameter
Power Dissipation
Power Dissipation*
Thermal Resistance
(Junction to Ambient)
VDD Accuracy @ 0.8 mA
Softstart Charging Current
Thermal Shutdown
Thermal Shutdown Hysteresis
Notes:
1. Transient surge defined in IEC60060 as a 1000 V impulse of either polarity applied to CT1–CT2 or SP1–SP2. The
2. The classification currents are guaranteed only when recommended RCLASS resistors are used, as specified in
3. IPORT includes full operating current of switching regulator controller.
4. The PD interface includes dual-level input current limit. At turn-on, before the HSO load capacitor is charged, the
5. See “AN296: Using the Si3400/1/2 PoE PD Controller in Isolated and Non-Isolated Designs” for more information.
6. Applies to non-isolated applications only (VOUT on schematic in Figure 1).
or in thermally-constrained applications. For more information, see “AN313: Using the Si3401/2 in High Power
Applications”.
shape of the impulse shall have a 300 ns full rise time and a 50 µs half fall time with 201  source impedance.
Table 11.
current limit is set at the inrush level. After the capacitor has been charged within ~1.25 V of VNEG, the operating
current limit is engaged. This higher current limit remains active until the UVLO lower limit has been tripped or until the
hotswap switch is sufficiently current-limited to cause a foldback of the HSO voltage.
VPORT = 50 V, V
VPORT = 50 V, V
bridges bypassed
Symbol

JA
Condition
OUT
OUT
36 V < VPORT < 57 V
Junction temperature
= 5 V, 2 A
= 5 V, 2 A w/ diode
Still air; assumes a minimum of
nine thermal vias are connected
to a 2 in
for the package “pad” node
(VNEG).
ISOSSFT pin
Description
SSFT pin
Rev. 1.1
Test Condition
2
heat spreader plane
Min
—
—
Min
4.5
—
—
—
—
Typ
1.2
0.7
Typ
160
25
13
—
—
Typ
44
Max
—
—
Max
5.5
25
—
—
—
Units
°C/W
Units
Unit
W
W
µA
µA
ºC
ºC
V