IRS26302DJPBF International Rectifier, IRS26302DJPBF Datasheet - Page 22

• Manufacturer Part Number: IRS26302DJPBF
• Description: IC BRIDGE +1 GATE DVR 3PH 44PLCC
• Manufacturer: International Rectifier

Specifications of IRS26302DJPBF

• Configuration: 3 Phase Bridge
• Input Type: Non-Inverting
• Delay Time: 320ns
• Current - Peak: 200mA
• Number Of Configurations: 1
• Number Of Outputs: 3
• High Side Voltage - Max (bootstrap): 600V
• Voltage - Supply: 10 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC (32 Leads)
• Number Of Drivers: 6
• Driver Configuration: Non-Inverting
• Driver Type: High and Low Side
• Input Logic Level: CMOS/TTL
• Rise Time: 190ns
• Fall Time: 75ns
• Propagation Delay Time: 710ns
• Peak Output Current: 350mA
• Power Dissipation: 4.6W
• Operating Supply Voltage (min): 10V
• Turn Off Delay Time: 50ns
• Turn On Delay Time (max): 50ns
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Fault Reporting and Programmable Fault Clear Timer
The IRS26302DJ provides an integrated fault reporting output and an adjustable fault clear timer. There are several
situations that would cause the HVIC to report a fault via the FAULT pin: an undervoltage condition of V
Ground Fault (GF), PCFtrip pin recognizes an overcurrent. Once the fault condition occurs, the FAULT pin is
internally pulled to V
condition has been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on the
FAULT pin will return to V
The length of the fault clear time period (t
where the time constant is set by R
(ITRIP), RCIN and FAULT are pulled to V
Figure 13 shows that R
and V
The design guidelines for this network are shown in Table 3.
www.irf.com
Figure 12: RCIN and FAULT pin waveforms
SS
pins.
SS
RCIN
and the fault clear timer is activated. The fault output stays in the low state until the fault
CC
is connected between the V
.
Figure 11: Output enable/disable timing waveform
RCIN
FLTCLR
and C
SS
, and once the fault has been removed, the fault clear timer begins.
Table 3: Design guidelines
C
R
) is determined by exponential charging characteristics of the capacitor
RCIN
RCIN
RCIN
. In Figure 12 where we see that a fault condition has occurred
CC
22
and the RCIN pin, while C
0.5 M to 2 M
Figure 13: Programming the fault clear timer
1 nF, ceramic
>> R
ON,RCIN
RCIN
is placed between the RCIN
© 2009 International Rectifier
IRS26302DJ
CC
or ITRIP,