MAX17480GTL+ Maxim Integrated Products, MAX17480GTL+ Datasheet - Page 18

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MAX17480GTL+

Manufacturer Part Number
MAX17480GTL+
Description
IC CTRLR SERIAL VID 40-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX17480GTL+

Applications
Processor
Current - Supply
5mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
40-TQFN Exposed Pad
Output Voltage Range
- 10 V to + 10 V
Input Voltage Range
4 V to 26 V
Input Current
5 mA
Power Dissipation
1778 mW
Operating Temperature Range
- 40 C to + 105 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AMD 2-/3-Output Mobile Serial
VID Controller
18
______________________________________________________________________________________
PIN
20
21
22
23
24
25
26
27
28
29
30
31
32
PWRGD
NAME
THRM
BST2
BST1
DH2
DH1
DL2
DL1
LX2
V
LX1
V
DD
CC
Open-Drain Power-Good Output. PWRGD is the wired-OR open-drain output of all three SMPS
outputs.
PWRGD is forced high impedance whenever the slew-rate controller is active (output voltage
transitions).
During startup, PWRGD is held low for an additional 20µs after the MAX17480 reaches the startup
boot voltage set by the SVC and SVD pins. The MAX17480 stores the boot VID when PWRGD first
goes high. The stored boot VID is cleared by rising
PWRGD is forced low in shutdown.
When SMPS is in pulse-skipping mode, the upper PWRGD threshold comparator for the respective
SMPS is blanked during a downward VID transition. The upper PWRGD threshold comparator is re-
enabled once the output is in regulation (Figure 6).
SMPS2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.
SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to SMPS2’s zero-crossing comparator.
Boost Flying Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between
V
SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to V
DL2 is also forced high when an output overvoltage fault is detected. DL2 is forced low in skip
mode after an inductor current zero crossing (GND2 - LX2) is detected.
Supply Voltage Input for the DL_ Drivers. V
the BST_ flying capacitors during the off-time. Connect V
voltage. Bypass V
SMPS1 Low-Side Gate-Driver Output. DL1 swings from GND1 to V
DL1 is also forced high when an output overvoltage fault is detected. DL1 is forced low in skip
mode after an inductor current zero crossing (GND1 - LX1) is detected.
Boost Flying Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between
V
SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to SMPS1’s zero-crossing comparator.
SMPS1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.
Active-Low Open-Drain Output of Internal Comparator.
THRM goes below 1.5V (30% of V
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V
and GND) to THRM. Select the components so the voltage at THRM falls below 1.5V (30% of V
at the desired high temperature.
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with a 1µF minimum
capacitor. A V
cleared by cycling V
DD
DD
and BST2 charges the flying capacitor during the time the low-side FET is on.
and BST1 charges the flying capacitor during the time the low-side FET is on.
CC
UVLO event that occurs while the IC is functioning is latched, and can only be
DD
CC
to GND with a 2.2µF or greater ceramic capacitor.
power or by toggling
CC
).
DD
FUNCTION
is high impedance in shutdown.
is also the supply voltage used to internally recharge
.
Pin Description (continued)
DD
.
to the 4.5V to 5.5V system supply
is pulled low when the voltage at
DD
DD
. DL2 is forced low in shutdown.
. DL1 is forced low in shutdown.
CC
CC
)

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