MAX17480GTL+ Maxim Integrated Products, MAX17480GTL+ Datasheet - Page 28

• Manufacturer Part Number: MAX17480GTL+
• Description: IC CTRLR SERIAL VID 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480GTL+

• Applications: Processor
• Current - Supply: 5mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage Range: - 10 V to + 10 V
• Input Voltage Range: 4 V to 26 V
• Input Current: 5 mA
• Power Dissipation: 1778 mW
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AMD 2-/3-Output Mobile Serial
VID Controller
The nominal no-load output voltage (V
SMPS is defined by the selected voltage reference (VID
DAC) plus the remote ground-sense adjustment
(V
the following equation:
where V
SMPS DAC, V
age for core supplies, and V
set enabled by the OPTION pin when the PSI_L is set
high for core supplies.
The nominal output voltage (V
defined by the selected voltage reference (VID DAC)
plus the offset voltage (V
following equation:
where V
and V
Inside the MAX17480 are three 7-bit digital-to-analog
converters (DACs). Each DAC can be individually pro-
grammed to different voltage levels by the serial-inter-
face bus. The DAC sets the target for the output voltage
for the core and NB SMPSs. The available DAC codes
and resulting output voltages are compatible with the
AMD SVI (Table 4) specifications.
On startup, the MAX17480 slews the target for all three
DACs from ground to the boot voltage set by the SVC
and SVD pin-voltage levels. While the output is still below
regulation, the SVC and SVD levels can be changed,
and the MAX17480 sets the DACs to the new boot volt-
age. Once the programmed boot voltage is reached and
PWRGD goes high, the MAX17480 stores the boot VID.
Changes in the SVC and SVD settings do not change the
output voltage once the boot VID is stored. When
PGD_IN goes high, the MAX17480 exits boot mode, and
the three DACs can be independently set to any voltage
in the VID table by the serial interface.
If PGD_IN goes from high to low any time after the boot
VID is stored, the MAX17480 sets all three DACs back
to the voltage of the stored boot VID.
Table 3 is the boot voltage code table.
28
GNDS
______________________________________________________________________________________
OFFSET_NB
V
TARGET
V
) and the offset voltage (V
DAC
DAC
TARGET
Nominal Output-Voltage Selection
is the selected VID voltage of the NB DAC,
is the selected VID voltage of the core
GNDS
=
3
V
is +12.5mV.
=
FBDC
V
is the ground-sense correction volt-
OUT
=
3
OFFSET_NB
V
=
Core SMPS Output Voltage
DAC
V
OFFSET
NB SMPS Output Voltage
DAC
+
TARGET
V
OFFSET
+
GNDS
V
is the +12.5mV off-
) as defined in the
OFFSET NB
TARGET
) for the NB is
+
) as defined in
Boot Voltage
V
OFFSET
_
7-Bit DAC
) for each
A +12.5mV offset can be added to both core SMPS
DAC voltages for applications that include DC droop.
The offset is applied only after the MAX17480 exits boot
mode (PGD_IN going from low to high), and the
MAX17480 enters the serial-interface mode. The offset
is disabled when the PSI_L bit is set, saving more
power when the load is light.
The OPTION pin setting enables or disables the
+12.5mV offset. Connect OPTION to OSC (2V) or GND
to enable the offset. Keep OPTION connected to 3.3V
or V
Address Change for Core SMPSs (OPTION) section.
The NB SMPS output has a -5.5mV/A load line. A
+12.5mV offset is added to keep the output within regu-
lation over the full load. See the Offset and Current-
Limit Setting for NB SMPS (ILIM3) section.
The MAX17480 performs positive voltage transitions in
a controlled manner, automatically minimizing input
surge currents. This feature allows the circuit designer
to achieve nearly ideal transitions, guaranteeing just-in-
time arrival at the new output-voltage level with the low-
est possible peak currents for a given output
capacitance. The slew rate (set by resistor R
be set fast enough to ensure that the transition is com-
pleted within the maximum allotted time for proper CPU
operation. R
responding slew rates between 25mV/µs to 2.5mV/µs,
respectively, for the SMPSs.
At the beginning of an output-voltage transition, the
MAX17480 blanks both PWRGD comparator thresholds,
preventing the PWRGD open-drain output from chang-
ing states during the transition. At the end of an upward
VID transition, the controller enables both PWRGD
thresholds approximately 20µs after the slew-rate
controller reaches the target output voltage. At the end
Table 3. Boot Voltage Code Table
SVC
0
0
1
1
CC
to disable the offset. See the Offset and
TIME
Output-Voltage Transition Timing
SVD
0
1
0
1
is between 35.7kΩ and 357kΩ for cor-
SMPS Output-Voltage Transition
BOOT VOLTAGE
V
OUT
Core SMPS Offset
1.1
1.0
0.9
0.8
NB SMPS Offset
(V)
TIME
) must