MAX17480GTL+ Maxim Integrated Products, MAX17480GTL+ Datasheet - Page 37

• Manufacturer Part Number: MAX17480GTL+
• Description: IC CTRLR SERIAL VID 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480GTL+

• Applications: Processor
• Current - Supply: 5mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage Range: - 10 V to + 10 V
• Input Voltage Range: 4 V to 26 V
• Input Current: 5 mA
• Power Dissipation: 1778 mW
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Adaptive dead-time circuits monitor the DL and DH dri-
vers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL and DH drivers to the MOSFET gates
for the adaptive dead-time circuits to work properly;
otherwise, the sense circuitry in the MAX17480 inter-
prets the MOSFET gates as “off” while charge actually
remains. Use very short, wide traces (50 mils to 100
mils wide if the MOSFET is 1in from the driver).
The internal pulldown transistor that drives DL low is
robust, with a 0.25Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up due to capacitive coupling
from the drain to the gate of the low-side MOSFETs
when the inductor node (LX) quickly switches from
ground to V
long inductive driver traces could require rising LX
edges that do not pull up the low-side MOSFET’s gate,
causing shoot-through currents. The capacitive coupling
between LX and DL created by the MOSFET’s gate-to-
drain capacitance (C
(C
exceed the following minimum threshold:
Typically, adding a 4700pF capacitor between DL and
power ground (C
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
Alternatively, shoot-through currents can be caused by
a combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ω in series with BST
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading the
turn-off time (R
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
The +12.5mV offset and the address change features
of the MAX17480 can be selectively enabled and dis-
abled by the OPTION pin setting. When the offset is
ISS
- C
RSS
IN
), and additional board parasitics should not
. Applications with high input voltages and
BST
V
NL
______________________________________________________________________________________
GS TH
Offset and Address Change
in Figure 11), close to the low-side
(
in Figure 11). Slowing down the
RSS
for Core SMPSs (OPTION)
)
), gate-to-source capacitance
>
V
IN
⎛
⎜
⎝
C
C
RSS
ISS
⎞
⎟
⎠
AMD 2-/3-Output Mobile Serial
enabled, setting the PSI_L bit to 0 disables the offset,
reducing power consumption in the low-power state.
See the Core SMPS Offset section for a detailed
description of this feature.
In addition, the address of the core SMPSs can be
exchanged, allowing for flexible layout of the MAX17480
with respect to the CPU placement on the same or
opposite sides of the PCB. Table 5 shows the OPTION
pin voltage levels and the features that are enabled.
Figure 11. Gate-Drive Circuit
Note: VDD0 refers to CORE0 and VDD1 refers to CORE1 for
the AMD CPU.
Table 5. OPTION Pin Settings
OPTION
(R
(C
BST
GND
3.3V
V
NL
2V
CC
)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
)* OPTIONAL—THE CAPACITOR REDUCES LX-TO-DL CAPACITIVE
MAX17480
ENABLES
THE SWITCHING NODE RISE TIME.
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
OFFSET
0
0
1
1
PGND
BST
V
DH
LX
DD
DL
VID Controller
(R
C
BST
BYP
BIT 1 (VDD0)
BIT 2 (VDD1)
BIT 1 (VDD0)
BIT 2 (VDD1)
)*
ADDRESS
SMPS1
C
(C
BST
NL
)*
N
N
H
L
BIT 2 (VDD1)
BIT 1 (VDD0)
BIT 2 (VDD1)
BIT 1 (VDD0)
ADDRESS
SMPS2
INPUT (V
L
IN
)
37