MAX17480GTL+ Maxim Integrated Products, MAX17480GTL+ Datasheet - Page 9

• Manufacturer Part Number: MAX17480GTL+
• Description: IC CTRLR SERIAL VID 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480GTL+

• Applications: Processor
• Current - Supply: 5mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage Range: - 10 V to + 10 V
• Input Voltage Range: 4 V to 26 V
• Input Current: 5 mA
• Power Dissipation: 1778 mW
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, V
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T
noted. Typical values are at T
FAULT DETECTION
Output Overvoltage Trip
Threshold
(SMPS1 and SMPS2 Only)
Output Undervoltage Protection
Trip Threshold
PWRGD Threshold
PWRGD, Output Low Voltage
GATE DRIVERS
DH_ Gate-Driver On-Resistance
DL_ Gate-Driver On-Resistance
Dead Time
Internal BST1, BST2 Switch R
Internal BST3 Switch R
2-WIRE I
SVI Logic-Input Threshold
SVC Clock Frequency
START Condition Hold Time
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold
, Output Low Voltage
Trip Threshold
2
PARAMETER
C BUS LOGIC INTERFACE
_______________________________________________________________________________________
IN
ON
= 12V, V
A
ON
= +25°C.) (Note 5)
CC
= V
SYMBOL
R
R
t
t
t
t
t
t
V
ON(DH
SU;STO
HD;DAT
ON(DL
SU;STA
SU;STA
DH
DL
V
f
OVP_
DD
SVC
UVP
_
_
DH
DL
= V
_
_
)
)
IN3
Measured at
FBDC_, rising edge
Measured at FBDC_ or OUT3 with respect
to unloaded output voltage
Measured at FBDC_
or OUT3 with respect
to unloaded output
voltage, 15mV
hysteresis (typ)
I
Measured at THRM, with respect to V
falling edge, 115mV hysteresis (typ)
I
BST_ - LX_ forced to
5V (Note 4)
DL_, high state
DL_, low state
DH_ low to DL_ high
DL_ low to DH_ high
BST1, BST2 to V
BST3 to V
SVC, SVD, rising edge, hysteresis = 0.14 x
V
A master device must internally provide a
hold time of at least 300ns for the SVD signal
(referred to the V
the undefined region of SVC’s falling edge
AMD 2-/3-Output Mobile Serial
SINK
SINK
DDIO
= SHDN = PGD_IN = 5V, V
= 4mA
= 4mA
(V)
DD
, I
BST3
CONDITIONS
IHMIN
DD
, I
= 10mA
BST1
of SVC signal) to bridge
PWM mode
Skip mode and
output have not
reached the
regulation voltage
Lower threshold,
falling edge
(undervoltage)
Upper threshold,
rising edge
(overvoltage)
High state (pullup)
Low state (pulldown)
= I
BST2
DDIO
= 10mA
= 1.8V, OPTION = GNDS_ = AGND = PGND,
CC,
A
VID Controller
= -40°C to +105°C, unless otherwise
V
+150
0.3 x
-450
-350
1.80
29.5
MIN
250
160
160
160
DDIO
9
9
TYP
V
+250
MAX
0.7 x
-350
-250
1.90
30.5
350
DDIO
0.4
0.4
2.5
2.5
2.0
0.6
3.4
35
35
20
20
70
UNITS
MHz
mV
mV
mV
ns
ns
ns
ns
ns
%
V
V
V
V
9