MAX17480GTL+ Maxim Integrated Products, MAX17480GTL+ Datasheet - Page 35

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MAX17480GTL+

Manufacturer Part Number
MAX17480GTL+
Description
IC CTRLR SERIAL VID 40-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX17480GTL+

Applications
Processor
Current - Supply
5mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
40-TQFN Exposed Pad
Output Voltage Range
- 10 V to + 10 V
Input Voltage Range
4 V to 26 V
Input Current
5 mA
Power Dissipation
1778 mW
Operating Temperature Range
- 40 C to + 105 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 9. PGD_IN Timing
Figure 10. THRM Configuration
When SHDN goes low, the MAX17480 enters shutdown
mode. PWRGD is pulled low immediately and forces all
DH and DL low, and all three outputs are discharged
through the 20Ω internal discharge FETs through the CSN
pin for core SMPSs and through the OUT3 pin for NB
SMPSs.
The MAX17480 features an independent comparator with
an accurate threshold (V
ply voltage (V
tor-divider between V
PLACE R
HOTTEST POWER COMPONENT.
(HIGH DAC TARGET)
(LOW DAC TARGET)
NTC
SMPS V
SMPS V
NEXT TO THE
SVC/SVD
PGD_IN
VRHOT Temperature Comparator
PWRGD
HOT
PSI_L
OUT
OUT
= 0.3V
______________________________________________________________________________________
HOT
CC
CC
R
THRM
R
NTC
). Use a resistor- and thermis-
BUS IDLE
) that tracks the analog sup-
TARGET
and GND to generate a
V
THRM
GND
CC
MAX17480
HIGH-Z
BLANK
Shutdown
AMD 2-/3-Output Mobile Serial
2-BIT BOOT VID, SVC/SVD INPUTS DISABLED
20µs
V
OUT
PLACE R
NEXT TO THE RESPECTIVE SMPS'S
POWER COMPONENT.
PULSE-SKIPPING MODE
PTC1
voltage-SMPS overtemperature monitor. Place the thermis-
tor as close as possible to the MOSFETs and inductors.
Place three individual thermistors near to each SMPS to
monitor the temperature of the respective SMPS. When
core SMPSs are in combined-mode operation, the cur-
rent-balance circuit balances the currents between
core SMPS phases. As such, the power loss and heat
in each phase should be identical, apart from the
effects of placement and airflow over each phase.
Single thermistors can be placed near either of the
phases and still be effective for core SMPS temperature
monitoring, and one thermistor can be saved. See
Figure 10.
, R
PTC2
, AND R
PTC3
R
PTC2
VID Controller
R
PTC3
R
R
THRM
PTC1
HIGH-Z
BLANK
V
THRM
GND
CC
BUS IDLE
20µs
MAX17480
35

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