LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 41

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

Register
Address
Register
Address
Register
Address
Register
Address
16.4.2 Registers 08–09h and 54–55h Filtered Temperature Value Registers
These registers reflect the temperature of zones 1 and 2 after the spike smoothing filter has been applied.
The characteristics of the filtering can be adjusted by using the Zones 1/2 Spike Smoothing Control register.
16.4.3 Register 0Ah and 0Bh PWM1 and PWM2 8-bit Duty Cycle Value
These registers report the current duty cycle being driven on the PWM1 or PWM2 outputs. It is the upper 8 bits of the 9-bit PWM
value. It reflects the maximum duty cycle of any low-resolution or high-resolution PWM sources bound to the PWM1 or PWM2
outputs.
16.5 PWM Duty Cycle Overide Registers
16.5.1 Register 0Ch PWM1 Duty Cycle Override (low byte)
If manual PWM1 override is enabled in this register, all other PWM1 bindings are disabled except for the 100% override in the
LM96194 Status Control register (E2h).
16.5.2 Register 0Dh PWM1 Duty Cycle Override (high byte)
0Dh
0Ch
0Ah
0Bh
08h
09h
54h
55h
Bit
5:0
6
7
Read/
Write
Read/
Write
R/W
Read/
Write
R/W
Read/
Write
R
R
R
R
R
R
PWM1_EN_Hres_Over
PWM1 Duty Cycle
Override (low byte)
PWM1_DC[0]
PWM1 Duty Cycle
Register Name
Register
Override (high
Register Name
PWM1
PWM2
Name
Cycle
Value
Cycle
Value
Duty
Duty
Name
RES
Zone 2b (MMBT3904)
Zone 2a (MMBT3904)
byte)
Zone 1b (CPU)
Zone 1a (CPU)
Filtered Temp
Filtered Temp
Filtered Temp
Filtered Temp
Register
Name
Bit 7
7
7
Bit 7
PWM1_
DC[0]
Bit 7
Bit 6
6
6
R/W
R/W
R/W
R
Bit 6
EN_Hres
PWM1_
_Over
Bit 7
Bit 6
7
7
7
7
Bit 5
Description
Reserved
When this bit is set, high-resolution override for PWM1 is enabled. When
this bit is set, PWM1 will run at the programmed duty cycle: PWM1_DC
[8:0]/256 * 100%; values over 100h are reserved.
When this bit is set, bit [0] of the override duty cycle for PWM1 is set.
5
5
Bit 5
Bit 6
41
6
6
6
6
Bit 5
RES
Bit 4
4
4
Bit 5
PWM1_DC[8:1]
Bit 4
5
5
5
5
Bit 4
RES
Bit 3
Bit 4
3
3
4
4
4
4
Bit 3
Bit 3
RES
Bit 3
3
3
3
3
Bit 2
2
2
Bit 2
Bit 2
RES
Bit 2
2
2
2
2
Bit 1
1
1
Bit 1
Bit 1
RES
Bit 1
1
1
1
1
Bit 0
Bit 0
Bit 0
RES
Bit 0
0
0
0
0
0
0
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Default
Default
Default
Value
Default
Value
Value
Value
00h
00h
00h
00h
00h
00h
00h
00h