LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 97

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

Register
Address
Register
Address
16.15 OTHER MASK REGISTERS
16.15.1 Register ECh GPI Error Mask
These bits mask the corresponding bits in the B_ and H_GPI Error Status Registers. They do not effect the GPI State register.
16.15.2 Register EDh Miscellaneous Error Mask
ECh
EDh
Read/
Read/
Write
Write
R/W
R/W
1:2
7:6
Bit
0
3
4
5
Bit
0
1
2
3
4
5
6
7
DVccp_MSK
SCSI_MSK
VRD_MSK
GPI Error
Register
Miscellaneous
Name
Name
Mask
RES
RES
RES
Error Mask
Register
GPI0_MSK
GPI1_MSK
GPI2_MSK
GPI3_MSK
GPI4_MSK
GPI5_MSK
GPI6_MSK
GPI7_MSK
Name
Name
_MSK
Bit 7
GPI7
R/W
R/W
R/W
R/W
R/W
R/W
R
Bit 7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
_MSK
Bit 6
GPI6
RES
When this bit is set, VRD_HOT error events are masked.
RESERVED
When this bit is set, GPI8 error events are masked.
When this bit is set, dynamic Vccp limit error events for AD_IN7
(CPU1) are masked.
RESERVED. Leave "HIGH" for proper operation of the part.
Reserved
Bit 6
When this bit is set, GPI0 error events are masked.
When this bit is set, GPI1 error events are masked.
When this bit is set, GPI2 error events are masked.
When this bit is set, GPI3 error events are masked.
When this bit is set, GPI4 error events are masked.
When this bit is set, GPI5 error events are masked.
When this bit is set, GPI6 error events are masked.
When this bit is set, GPI7 error events are masked.
_MSK
GPI5
Bit 5
Bit 5
RES
97
_MSK
GPI4
Bit 4
DVccp
_MSK
Bit 4
Description
Description
_MSK
GPI3
Bit 3
SCSI1
_MSK
Bit 3
_MSK
GPI2
Bit 2
Bit 2
RES
_MSK
GPI1
Bit 1
Bit 1
RES
_MSK
_MSK
GPI0
Bit 0
VRD
Bit 0
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Default
Default
Value
Value
FFh
3Fh