ISL8101IRZ Intersil, ISL8101IRZ Datasheet - Page 14

• Manufacturer Part Number: ISL8101IRZ
• Description: IC PWM CTRLR BUCK 2PHASE 24-QFN
• Manufacturer: Intersil

Specifications of ISL8101IRZ

• Applications: Controller, Intel VRM9, VRM10, and AMD Hammer Applications
• Voltage - Input: 4.6 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.6 ~ 2.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. Equations 13 and 14 describe the
frequency response of the modulator (G
compensation (G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 9 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log-log graph of Figure 9 by adding the modulator gain, G
(in dB), to the feedback compensation gain, G
equivalent to multiplying the modulator transfer function and the
G
F
F
G
G
4. Calculate R
3. Calculate C
Z1
Z2
MOD
CL
FB
F
(typically, 0.5 to 1.0 times F
per-channel switching frequency. Change the numerical
factor to reflect desired placement of this pole. Placement
of F
compensation network at high frequency, in turn reducing
the HF ripple component at the COMP pin and minimizing
resultant duty cycle jitter.
C
f ( )
R
C
f ( )
=
=
LC
2
3
3
f ( )
------------------------------ -
2π R
-------------------------------------------------
2π
=
. Calculate C
P2
=
=
=
=
⋅
=
⋅
⋅
G
--------------------------------------------------- - ⋅
s f ( ) R
------------------------------------------------------- -
2π R
------------------------------------------------------------------------------------------------------------------------ -
(
--------------------- -
------------------------------------------------ -
2π R
F
----------- - 1
F
(
lower in frequency helps reduce the gain of the
1
d
----------------------------- -
1
MOD
1
R
SW
LC
2
+
MAX
R
⋅
+
1
⋅
⋅
V
⋅
s f ( ) R
1
1
+
s f ( ) R
C
2
3
–
OSC
2
3
f ( ) G
1
R
1
such that F
(see Equation 12) such that F
⋅
FB
⋅
⋅
⋅
3
C
1
⋅
0.7 F
C
V
⋅
⋅
(
) C
1
) and closed-loop response (G
IN
C
1
⋅
3
1
3
⋅
2
1
FB
⋅
such that F
+
F
⋅
⋅
P2
⋅
3
+
C
----------------------------------------------------------------------------------------
1
CE
s f ( )
C
SW
f ( )
C
3
+
F
1
against the capabilities of the error
2
)
P1
–
s f ( )
)
⋅
P1
⋅
1
⎛
⎜
⎝
(
14
1
R
=
is placed at F
⋅
+
F
1
SW
(
---------------------------------------------
2π R2
P2
1
CL
+
s f ( ) R
E
P2
where s f ( )
+
R
+
). F
⋅
, is constructed on the
=
s f ( ) E C
3
is placed below F
D
⋅
) C
------------------------------ -
2π R
) C
⋅
SW
⋅
2
1
⋅
⋅
,
MOD
-------------------- -
C
3
⋅
⋅
C
⎛
⎜
⎝
+
1
1
represents the
1
⋅
-------------------- -
C
C
3
CE
+
s
⋅
FB
1
1
⋅
2
C
C
), feedback
=
Z2
+
C
f ( ) L C
⋅
.
2
2
C
(in dB). This is
C
3
2π f j
is placed at
⋅
2
2
⎞
⎟
⎠
⋅ ⋅
⎞
⎟
⎠
CL
⋅
(EQ. 14)
(EQ. 11)
SW
(EQ. 13)
(EQ. 12)
):
MOD
ISL8101
ISL8101
compensation transfer function and then plotting the resulting
gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the per-channel switching frequency, F
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
MOSFETs
Given the fixed switching frequency of the ISL8101 and the
integrated output drives, the selection of MOSFETs revolves
closely around the current each MOSFET is required to
conduct, the capability of the devices to dissipate heat, as well
as the characteristics of available heat sinking. Since the
ISL8101 drives the MOSFETs with 5V, the selection of
appropriate MOSFETs should be done by comparing and
evaluating their characteristics at this specific V
voltage.
LOWER MOSFET POWER CALCULATION
Since virtually all of the heat loss in the lower MOSFET is
conduction loss (due to current conducted through the
channel resistance, r
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
0
LOG
20
log
⎛
⎜
⎝
R
-------
R
2
2
⎞
⎟
⎠
F
Z1
DS(ON)
F
F
LC
Z2
), a quick approximation for heat
F
F
CE
P1
F
0
F
20
P2
log
SW
G
CL
COMPENSATION GAIN
d
---------------------------------
OPEN LOOP E/A GAIN
.
CLOSED LOOP GAIN
MAX V
G
V
MODULATOR GAIN
MOD
OSC
FREQUENCY
GS
⋅
IN
bias
July 28, 2008
G
FB
FN9223.1