KS8995MA Micrel Inc, KS8995MA Datasheet
KS8995MA
Specifications of KS8995MA
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KS8995MA Summary of contents
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... All PHY units support 10BASE-T and 100BASE-TX. In addition, two of the PHY units support 100BASE-FX (KS8995MA is ports 4 and 5, KS8995FQ is port 3 and port 4). M9999-091508 ...
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... Control Reg I/F LED0[5:1] LED1[5:1] LED2[5:1] Notes: 1. KS8995MA has either TX copper or FX fiber for port 4 and port 5, other ports are the TX copper only. 2. KS8995FQ has either TX copper or FX fiber for port 3 and port 4, other ports are the TX copper only. Semptember 2008 10/100 10/100 ...
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... Ordering Information Part Number Standard Pb-Free KS8995MA KSZ8995MA KS8995FQ KSZ8995FQ KS8995MAI KSZ8995MAI KS8995FQI KSZ8995FQI Semptember 2008 • Per-port based software power-save on PHY (idle link detection, register configuration preserved) • QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based • ...
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Revision History Revision Date Summary of Changes 2.0 10/10/03 Created. 2.1 10/30/03 Editorial changes on electrical characteristics. 2.2 4/01/04 Editorial changes on the TTL input and output electrical characteristics. 2.3 1/19/05 Insert recommended reset circuit, pg. 70. Editorial, Pg. 36. ...
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Contents System Level Applications........................................................................................................................................... 8 Pin Configuration ........................................................................................................................................................ 10 Pin Description (by Number)...................................................................................................................................... 11 Pin Description (by Name) ......................................................................................................................................... 17 Introduction ................................................................................................................................................................. 23 Functional Overview: Physical Layer Transceiver .................................................................................................. 23 100BASE-TX Transmit.............................................................................................................................................. 23 100BASE-TX Receive............................................................................................................................................... 23 PLL Clock Synthesizer.............................................................................................................................................. 23 ...
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Register 6 (0x07): Global Control 4 .......................................................................................................................... 46 Register 7 (0x07): Global Control 5 .......................................................................................................................... 46 Register 8 (0x08): Global Control 6 .......................................................................................................................... 46 Register 9 (0x09): Global Control 7 .......................................................................................................................... 46 Register 10 (0x0A): Global Control 8........................................................................................................................ 47 Register ...
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Static MAC Address .................................................................................................................................................... 58 VLAN Address ............................................................................................................................................................. 60 Dynamic MAC Address............................................................................................................................................... 61 MIB Counters ............................................................................................................................................................... 62 MIIM Registers ............................................................................................................................................................. 65 Register 0: MII Control .............................................................................................................................................. 65 Register 1: MII Status ............................................................................................................................................... 65 Register 2: PHYID HIGH........................................................................................................................................... 66 Register 3: ...
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System Level Applications CPU WAN PHY & AFE (xDSL, CM...) Semptember 2008 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SPI/GPIO SPI Ethernet MAC MII-SW Ethernet MAC Figure 1. Broadband Gateway SPI/GPIO MII-SW ...
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Figure 4. Using KSZ8995FQ for Dual Media Converter or Fiber daisy chain connection Semptember 2008 10/100 10/100 MAC 1 PHY 1 10/100 10/100 PHY 2 MAC 2 10/100 10/100 MAC 3 PHY 3 10/100 10/100 MAC 4 PHY 4 10/100 ...
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Pin Configuration Semptember 2008 128-Pin PQFP 10 M9999-091508 ...
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Pin Description (by Number) Pin Number Pin Name 1 MDI-XDIS 2 GNDA 3 VDDAR 4 RXP1 5 RXM1 6 GNDA 7 TXP1 8 TXM1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA 13 TXP2 14 TXM2 15 VDDAR 16 GNDA ...
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... O 5 Physical transmit signal + (differential Physical transmit signal – (differential). P 2.5V or 3.3V analog V Fiber signal detect pin. FXSD5 is for port 5 of the KS8995MA. FXSD3 Ipd 5/3 is for port 3 of the KS8995FQ Ipd 4 Fiber signal detect pin for port 4. Gnd Analog ground. ...
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Pin Number Pin Name 61 PMRXDV 62 PMRXD3 63 PMRXD2 64 PMRXD1 65 PMRXD0 66 PMRXER 67 PCRS 68 PCOL 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 74 SMTXER 75 SMTXC 76 GNDD 77 VDDIO 78 SMRXC ...
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Pin Number Pin Name 82 SMRXD1 83 SMRXD0 84 SCOL 85 SCRS 86 SCONF1 87 SCONF0 88 GNDD 89 VDDC 90 LED5-2 91 LED5-1 Notes Power supply Input Output. I/O = Bidirectional. Gnd ...
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... Ipu All impedance state, a high-to-low transition to initiate the SPI data transfer; (2) not used in I Serial bus configuration pin. For this case, if the EEPROM is not present, the KS8995MA/FQ will start itself with the PS[1. default register values. Pin Configuration Ipd PS[1.0]=00 PS[1.0]=01 PS[1 ...
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... Semptember 2008 (1) Type Port Pin Function Ipd Serial bus configuration pin. See “Pin 113.” Ipu Reset the KS8995MA/FQ. Active low. Gnd Digital ground. P 1.8V digital core V Ipd NC for normal operation. Factory test pin. Ipd NC for normal operation. Factory test pin. ...
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Pin Description (by Name) Pin Number Pin Name 39 FXSD4 38 FXSD3/FXSD5 124 GNDA 42 GNDA 44 GNDA 2 GNDA 16 GNDA 30 GNDA 6 GNDA 12 GNDA 21 GNDA 27 GNDA 34 GNDA 40 GNDA 120 NC 127 GNDA ...
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Pin Number Pin Name 97 LED3-1 96 LED3-2 95 LED4-0 94 LED4-1 93 LED4-2 92 LED5-0 91 LED5-1 90 LED5-2 107 MDC 108 MDIO 1 MDI-XDIS 45 MUX1 46 MUX2 68 PCOL 67 PCRS 60 PMRXC 65 PMRXD0 64 PMRXD1 ...
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... Ipd 5 PHY[5] MII transmit error. Ipd Serial bus configuration pin. See “Pin 113.” Serial bus configuration pin. If EEPROM is not present, the Ipd KS8995MA/FQ will start itself with chip default (00)... Pin Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 Ipu Full-chip power down. Active low. ...
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Pin Number Pin Name 86 SCONF1 85 SCRS 78 SMRXC 83 SMRXD0 82 SMRXD1 81 SMRXD2 80 SMRXD3 79 SMRXDV 75 SMTXC 73 SMTXD0 72 SMTXD1 71 SMTXD2 70 SMTXD3 69 SMTXEN 74 SMTXER Notes Power supply. ...
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... Otri All master mode. See “Pin 113.” Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995MA/FQ is deselected and SPIQ is held in high Ipu All impedance state, a high-to-low transition to initiate the SPI data transfer; (2) not used for normal operation. Factory test pin. ...
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Pin Number Pin Name 89 VDDC 117 VDDC 59 VDDIO 77 VDDIO 100 VDDIO 121 X1 122 X2 Notes Power supply Input Output. Semptember 2008 (1) Type Port Pin Function P 1.8V digital ...
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... PHY may be accessed through the MII-P5 port. The KS8995MA/FQ has the flexibility to reside in a managed or unmanaged design managed design, a host processor has complete control of the KS8995MA/FQ via the SPI bus, or partial control via the MDC/MDIO interface. ...
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... Power Management The KS8995MA/FQ features a per port power down mode. To save power the user can power down ports that are not in use by setting port control registers or MII control registers. In addition, it also supports full chip power down mode ...
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... Register external pull-up or pull-down resistors on LED[5][2]. See “Register 3” section. Forwarding The KS8995MA/FQ will forward packets using an algorithm that is depicted in the following flowcharts. Figure 6 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and Semptember 2008 ...
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... The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8995MA/FQ flow controls a port that has just received a packet if the destination port resource is busy. The KS8995MA/FQ issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802 ...
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Semptember 2008 Start -Search VLAN table. NO VLAN ID PTF1=NULL -Ingress VLAN filtering VALID? -Discard NPVID check YES Search complete. FOUND Search based on Search Static Get PTF1 from DA or DA+FID Table static table. NOT FOUND Search complete. FOUND ...
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... Half-Duplex Back Pressure The KS8995MA/FQ also provides a half-duplex back pressure option (note: this is not in IEEE 802.3 standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, the KS8995MA/FQ sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber and excessive deference as defined in IEEE 802 ...
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... The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface betweenphysical layer and MAC layer devices. The KS8995MA/FQ provides two such interfaces. The MII-P5 interface is used to connectto the fifth PHY, whereas the MII-SW interface is used to connect to the fifth MAC. Each of these MII interfaces contains twodistinct groups of signals, one for transmission and the other for receiving ...
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... MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8995MA/FQ has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995MA has an MTXER pin, it should be tied low. ...
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... The processor may send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is disabled on the port in this state. Semptember 2008 Description Transmit Enable Serial Transmit Data Transmit Clock Collision Detection Carrier Sense Serial Receive Data Receive Clock Table 3. SNI Signals 31 KS8995MA/FQ Signal SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC M9999-091508 ...
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... KS8995MA/FQ internal look-up result. Normal packets should use this setting. If packets from the processors do not have a tag, the KS8995MA/FQ will treat them as normal packets and an internal look-up will be performed.The KS8995MA/FQ uses a non-zero “port mask” to bypass the look-up result and override any port setting, regardless of port states (blocking, disable, listening, learning) ...
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... Modify TPID to 0x810 + “port mask,” which indicates source port. No change to TCI, if VID is not null. Replace null VID with ingress port VID. Recalculate CRC. Insert TPID to 0x810 + “port mask,” which indicates source port. Insert TCI with ingress port VID. Recalculate CRC. Table 6. STPID Egress Rules (Switch to Processor) 33 KS8995MA/FQ M9999-091508 ...
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... A packet, received on port 1, is destined to port 4 after the internal look-up. The KS8995MA/FQ will forward the packet to port 4 only, since it does not meet the “AND” condition. A packet, received on port 1, is destined to port 2 after the internal look-up. The KS8995MA/FQ will forward the packet to both port 2 and port 5. ...
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... The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. The KS8995MA/FQ uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. ...
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... Configuration Interface The KS8995MA/FQ can function as a managed switch or unmanaged switch EEPROM or micro-controller exists, the KS8995MA/FQ will operate from its default setting. Some default settings are configured via strap in options as indicated in the table below. Pin # Pin Name 1 MDI-XDIS 45 MUX1 46 MUX2 62 PMRXD3 ...
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... LED indicator 1. Strap option: PU (default): enable PHY[5] MII I/F. PD: tristate all PHY[5] MII output. See “Pin 86 SCONF1.” Ipd Serial bus configuration pin. For this case, if the EEPROM is not present, the KS8995MA/FQ will start itself with the PS[1: default register values . Pin Configuration PS[1:0]=00 PS[1:0]=01 ...
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... SDA To configure the KS8995MA/FQ with a pre-configured EEPROM use the following steps the board level, connect pin 110 on the KS8995MA/FQ to the SCL pin on the EEPROM. Connect pin 111 on the KS8995MA/FQ to the SDA pin on the EEPROM. 2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00.” This puts the KS8995MA/FQ serial bus ...
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... Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure multiple read as shown in Figure 12. Note that read data is registered out of SPIQ on the falling edge of SPIC. 6. After configuration is written and verified, write a ‘1’ to Register 1 bit 0 to begin KS8995MA/FQ operation. Semptember 2008 Microprocessor Signal Description ...
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SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ READ COMMAND Semptember 2008 WRITE ADDRESS Figure 9. ...
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... Byte 2 MII Management Interface (MIIM) A standard MIIM interface is provided for all five PHY devices in the KS8995MA/FQ. An external device with MDC/MDIO capability is able to read PHY status or to configure PHY settings. The device is able to meet IEEE specification of 2.5MHz MDC clock. For details on the MIIM interface standard please reference the IEEE 802.3 specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in the KS8995MA/FQ. It can only access the standard MII registers. See “ ...
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Register Description Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F Port ...
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Global Registers Address Name Register 0 (0x00): Chip ID0 7-0 family ID Register 1 (0x01): Chip ID1 / Start Switch 7-4 Chip ID 3-1 Revision ID 0 Start Switch Register 2 (0x02): Global Control 0 7 Reserved 6-4 802.1p Base ...
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Address Name 5 IEEE 802.3x Transmit Flow Control Disable 4 IEEE 802.3x Receive Flow Control Disable 3 Frame Length Field Check 2 Aging Enable 1 fast age Enable 0 Aggressive Back Off Enable Register 4 (0x04): Global Control 2 7 ...
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Address Name 4 Flow Control and Back Pressure fair Mode 3 No Excessive Collision Drop 2 Huge Packet Support 1 Legal Maximum Packet Size Check Disable 0 Priority Buffer Reserve Register 5 (0x05): Global Control 3 7 802.1q VLAN Enable ...
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Address Name 1 Enable “Tag” Mask 0 Sniff Mode Select Register 6 (0x07): Global Control 4 7 Switch MII Back Pressure Enable 6 Switch MII Half-Duplex Mode 5 Switch MII Flow Control Enable 4 Switch MII 10BT 3 Null VID ...
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Address Name Register 10 (0x0A): Global Control 8 7-0 Factory Testing Register 11 (0x0B): Global Control 9 7-4 Reserved 3 PHY Power Save 2 Factory Setting 1 LED Mode 0 Special TIPD Mode Semptember 2008 Description Reserved N ...
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Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 ...
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Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 Register 81 (0x51): Port 5 Control 1 Address Name 7 Sniffer Port ...
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Address Name 3 Back Pressure Enable 2 Transmit Enable 1 Receive Enable 0 Learning Disable Note: Bits 2-0 are used for spanning tree support. See “Spanning Tree Support” section. Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port ...
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Register 21 (0x15): Port 1 Control 5 Register 37 (0x25): Port 2 Control 5 Register 53 (0x35): Port 3 Control 5 Register 69 (0x45): Port 4 Control 5 Register 85 (0x55): Port 5 Control 5 Address Name 7-0 Transmit High ...
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Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 Register 73 (0x49): Port 4 Control 9 Register 89 (0x59): Port 5 Control 9 Address Name 7-0 Receive Low ...
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Address Name 3 High Priority Receive Rate Flow Control Enable 2 Transmit Differential Priority Rate Control 1 Low Priority Transmit Rate Control Enable 0 High Priority Transmit Rate Control Enable Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): ...
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Address Name 0 Advertised 10BT Half- Duplex Capability Note: Port Control 12 and 13, and Port Status 0 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition. Register 29 (0x1D): Port 1 Control 13 Register ...
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Address Name 2 Partner 100BT Half- Duplex Capability 1 Partner 10BT Full-Duplex Capability 0 Partner 10BT Half-Duplex Capability Register 31 (0x1F): Port 1 Control 14 Register 47 (0x2F): Port 2 Control 14 Register 63 (0x3F): Port 3 Control 14 Register ...
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Address Name Register 101 (0x65): TOS Priority Control Register 5 7-0 DSCP[23:16] Register 102 (0x66): TOS Priority Control Register 6 7-0 DSCP[15:8] Register 103 (0x67): TOS Priority Control Register 7 7-0 DSCP[7:0] Registers 104 to 109 define the switching engine’s ...
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Address Name Register 113 (0x71): Indirect Data Register 7 63-56 Indirect Data Register 114 (0x72): Indirect Data Register 6 55-48 Indirect Data Register 115 (0x73): Indirect Data Register 5 47-40 Indirect Data Register 116 (0x74): Indirect Data Register 4 39-32 ...
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... Static MAC Address KS8995MA/FQ has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging, migration, and learning purposes. The static DA look-up result will have precedence over the dynamic DA look-up result ...
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Examples: (1) Static Address Table Read (read the 2nd entry) Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (60-56) Read Register 114 (55-48) Read ...
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... VID If 802.1q VLAN mode is enabled, KS8995MA/FQ assigns a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up. If the VID is not valid, the packet is dropped and no address learning occurs ...
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... Dynamic MAC Address This table is read only. The contents are maintained by the KS8995MA/FQ only. Address Name Format of Dynamic MAC Address Table (1K entries) 68 MAC Empty 67- Valid Entries 57-56 Time Stamp 55 Data Ready 54-52 Source Port 51-48 FID 47-0 MAC Address Examples: (1) Dynamic MAC Address Table Read (read the 1st entry), and retrieve the MAC table size ...
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MIB Counters The MIB counters are provided on per port basis. The indirect memory is as below: For Port 1 Offset Counter Name 0x0 RxLoPriorityByte 0x1 RxHiPriorityByte 0x2 RxUndersizePkt 0x3 RxFragments 0x4 RxOversize 0x5 RxJabbers 0x6 RxSymbolError 0x7 RxCRCerror 0x8 ...
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For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f) For port 4, the base is 0x60, same offset definition (0x60-0x7f) For port 5, the base is 0x80, ...
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MIB counter read (read port counter) Write to Register 110 with 0x1c (read MIB counter selected) Write to Register 111 with 0x2e (trigger the read operation) Then Read Register 117 (counter value 31-24) //If bit 31 ...
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MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for ...
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Address Name 3 AN Capable 2 Link Status 1 Jabber Test 0 Extended Capable Register 2: PHYID HIGH 15-0 Phyid High Register 3: PHYID LOW 15-0 Phyid Low Register 4: Advertisement Ability 15 Next Page 14 Reserved 13 Remote fault ...
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Absolute Maximum Ratings Supply Voltage ( .......................–0.5V to +2.4V DDAR DDAP DDC ( .................................–0.5V to +4.0V DDAT DDIO Input Voltage ........................................–0.5V to +4.0V Output Voltage .....................................–0.5V to +4.0V Lead Temperature (soldering, 10 ...
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Symbol Parameter 10BASE-T Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer Peak Differential Output Voltage P Jitters Added Rise/fall Times Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device ...
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Timing Diagrams Receive Timing SCL SDA Figure 13. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 14. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time H1 ...
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Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 Semptember 2008 ts2 tcyc2 th2 Figure 15. SNI Input Timing tcyc2 ...
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Symbol Parameter t RXC Period P t RXC Pulse Width WL t RXC Pulse Width WH t RXD [3:0], RXDV Set-up to Rising Edge of RXC SU t RXD [3:0], RXDV Hold from Rising Edge of RXC HD t CRS ...
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Symbol Parameter t TXD [3:0] Set-up to TXC High SU1 t TXEN Set-up to TXC High SU2 t TXD [3:0] Hold after TXC High HD1 t TXER Hold after TXC High HD2 t TXEN High to CRS Asserted Latency CRS1 ...
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SPIS_N tCHSL SPIC tDVCH SPID SPIQ Symbol Parameter f Clock Frequency C t SPIS_N Inactive Hold Time CHSL t SPIS_N Active Set-Up Time SLCH t SPIS_N Active Hold Time CHSH t SPIS_N Inactive Set-Up Time SHCH t SPIS_N Deselect Time ...
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SPIS_N SPIC tCLQX SPIQ SPID Symbol Parameter f Clock Frequency C t SPIQ Hold Time CLQX t Clock Low to SPIQ Valid CLQV t Clock High Time CH t Clock Low Time CL t SPIQ Rise Time QLQH t SPIQ ...
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Supply Voltage RST_N Strap-In Value Strap-In / Output Pin Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC Semptember 2008 tsr tcs ...
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... CPU/FPGA provides warm reset after power up also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. Semptember 2008 VCC D1: 1N4148 D1 KS8995MA RST 10µF Figure 22. Recommended Reset Circuit VCC R ...
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Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common- mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio ...
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Package Information Semptember 2008 Pin # 128-Pin PQFP (PQ) 78 M9999-091508 ...
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 faX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is ...