KS8995MA Micrel Inc, KS8995MA Datasheet - Page 36

• Manufacturer Part Number: KS8995MA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995MA

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1017 - BOARD EVAL EXPERIMENT KS8995M
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

Semptember 2008
Configuration Interface
The KS8995MA/FQ can function as a managed switch or unmanaged switch. If no EEPROM or micro-controller
exists, the KS8995MA/FQ will operate from its default setting. Some default settings are configured via strap in
options as indicated in the table below.
Notes:
1.
Pin #
45
46
62
63
64
65
66
67
68
80
81
82
83
1
NC = No connect.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Fulld = Full duplex.
Pin Name
MDI-XDIS
PMRXER
PMRXD3
PMRXD2
PMRXD1
PMRXD0
SMRXD3
SMRXD2
SMRXD1
SMRXD0
MUX1
MUX2
PCRS
PCOL
PU/PD
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
NC
NC
Ipd
(1)
Description
Disable auto MDI/MDI-X.
PD = (default) = normal operation
PU = disable auto MDI/MDI-X on all ports.
Factory test pins. MUX1 and MUX2 should be left unconnected for normal
operation.
Mode
Normal Operation
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU =
disable flow control.
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU
= enable back pressure.
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision
packets; PU = does not drop excessive collision packets.
PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-
off algorithm in half-duplex mode; PU = enable for performance enhancement.
PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU =
packet size up to 1536 bytes.
PHY[5] MII carrier sense/strap option for port 4 only. PD (default) = force half-
duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto-
negotiation is disabled or fails. Refer to register 76.
PHY[5] MII collision detect/strap option for port 4 only. PD (default) = no force
flow control. PU = force flow control. Refer to register 66.
Switch MII receive bit 3. Strap option: PD (default) = disable switch MII full-
duplex flow control; PU = enable switch MII full-duplex flow control.
Switch MII receive bit 2. Strap option: PD (default) = switch MII in full-duplex
mode; PU = switch MII in half-duplex mode.
Switch MII receive bit 1. Strap option: PD (default) = switch MII in 100Mbps
mode; PU = switch MII in 10Mbps mode.
Switch MII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU =
mode 1. See “Register 11.”
LEDX_2
LEDX_1
LEDX_0
(1)
36
Fulld/Col
Mode 0
Lnk/Act
Speed
MUX1
NC
100Lnk/Act
10Lnk/Act
Mode 1
M9999-091508
Fulld
MUX2
NC