KS8995MA Micrel Inc, KS8995MA Datasheet - Page 15

• Manufacturer Part Number: KS8995MA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995MA

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1017 - BOARD EVAL EXPERIMENT KS8995M
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

Semptember 2008
Notes:
1.
Pin Number
100
101
102
103
104
105
106
107
108
109
110
111
112
113
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
NC = No connect.
92
93
94
95
96
97
98
99
SSPID/SDA
Pin Name
SPIC/SCL
SPIS_N
LED5-0
LED4-2
LED4-1
LED4-0
LED3-2
LED3-1
LED3-0
LED2-2
LED2-1
LED2-0
LED1-2
LED1-1
LED1-0
VDDIO
GNDD
MDIO
SPIQ
MDC
PS1
Type
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Gnd
Otri
Ipu
I/O
I/O
I/O
Ipu
Ipd
P
(1)
Port
All
All
All
All
All
All
5
4
4
4
3
3
3
2
2
2
1
1
1
Pin Function
LED indicator 0.
LED indicator 2.
LED indicator 1.
LED indicator 0.
LED indicator 2.
LED indicator 1.
LED indicator 0.
Digital ground.
3.3V digital V
LED indicator 2.
LED indicator 1.
LED indicator 0.
LED indicator 2.
LED indicator 1.
LED indicator 0.
Switch or PHY[5] MII management data clock.
Switch or PHY[5] MII management data I/O.
Features internal pull down to define pin state when not driven.
(1) SPI serial data output in SPI slave mode; (2) output clock at 61kHz
in I
(1) Input clock up to 5MHz in SPI slave mode; (2) output clock at 61kHz
in I
(1) Serial data input in SPI slave mode; (2) serial data input/output in
I
Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N
is high, the KS8995MA/FQ is deselected and SPIQ is held in high
impedance state, a high-to-low transition to initiate the SPI data
transfer; (2) not used in I
Serial bus configuration pin.
For this case, if the EEPROM is not present, the KS8995MA/FQ will
start itself with the PS[1.0] = 00 default register values.
Pin Configuration
PS[1.0]=00
PS[1.0]=01
PS[1.0]=10
PS[1.0]=11
2
C master mode. See “Pin 113.”
2
2
C master mode. See “Pin 113.”
C master mode. See “Pin 113.”
15
DD
for digital I/O.
2
C master mode.
Serial Bus Configuration
I
Reserved
SPI Slave Mode for CPU Interface
Factory Test Mode (BIST)
2
C Master Mode for EEPROM
M9999-091508