KS8995MA Micrel Inc, KS8995MA Datasheet - Page 26

• Manufacturer Part Number: KS8995MA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995MA

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1017 - BOARD EVAL EXPERIMENT KS8995M
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

Micrel, Inc.
KS8995MA/FQ
dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further
modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to
forward 2” (PTF2), as shown in Figure 7. This is where the packet will be sent.
KS8995MA/FQ will not forward the following packets:
• Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors.
• 802.3x pause frames. The KS8995MA/FQ will intercept these packets and perform the appropriate actions.
• “Local” packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches
the port where the packet was from, the packet is defined as “local.”
Switching Engine
The KS8995MA/FQ features a high-performance switching engine to move data to and from the MAC’s, packet
buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The
KS8995MA/FQ has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing
mode can be programmed through Register 2. See “Register 2.” In one mode, ports are allowed to use any free
buffers in the buffer pool. In the second mode, each port is only allowed to use 1/5 of the total buffer pool. There are
a total of 512 buffers available. Each buffer is sized at 128B.
Media Access Controller (MAC) Operation
The KS8995MA/FQ strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter-Packet Gap (IPG)
If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the
current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN.
Backoff Algorithm
The KS8995MA/FQ implements the IEEE Std. 802.3 binary exponential back-off algorithm, and optional “aggressive
mode” back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in
Register 3. See “Register 3.”
Late Collision
If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped.
Illegal Frames
The KS8995MA/FQ discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes
in Register 4. For special applications, the KS8995MA/FQ can also be programmed to accept frames up to 1916
bytes in Register 4. Since the KS8995MA/FQ supports VLAN tags, the maximum sizing is adjusted when these tags
are present.
Flow Control
The KS8995MA/FQ supports standard 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KS8995MA/FQ receives a pause control frame, the KS8995MA/FQ will not transmit the
next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received
before the current timer expires, the timer will be updated with the new value in the second pause frame. During this
period (being flow controlled), only flow control packets from the KS8995MA/FQ will be transmitted.
On the transmit side, the KS8995MA/FQ has intelligent and efficient ways to determine when to invoke flow control.
The flow control is based on availability of the system resources, including available buffers, available transmit
queues and available receive queues.
The KS8995MA/FQ flow controls a port that has just received a packet if the destination port resource is busy. The
KS8995MA/FQ issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard
802.3x. Once the resource is freed up, the KS8995MA/FQ sends out the other flow control frame (XON) with zero
pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is also provided to
prevent over-activation and deactivation of the flow control mechanism.
The KS8995MA/FQ flow controls all ports if the receive queue becomes full.
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Semptember 2008
M9999-091508