MT8VDDT6432UY-5K1 Micron Technology Inc, MT8VDDT6432UY-5K1 Datasheet - Page 10

• Manufacturer Part Number: MT8VDDT6432UY-5K1
• Description: MODULE DDR 256MB 100-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6432UY-5K1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 100-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
Serial Presence-Detect Operation
pdf: 09005aef80745603, source: 09005aef807455eb
DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN
The MT8VDDT3232U, MT8VDDT6432U, and MT8VDDT12832U are high-speed CMOS,
dynamic random-access, 128MB, 256MB, and 512MB memory modules organized in
x32 configuration. DDR SDRAM modules use internally configured quad-bank DDR
SDRAM devices.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effectively consists of a single 2n-bit
wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-
bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR
SDRAM during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the device bank and row to be accessed (BA0,
BA1 select devices bank; A0–A11 select device row for 128MB module, A0–A12 select
device row for 256MB and 512MB modules). The address bits registered coincident with
the READ or WRITE command are used to select the device bank and the starting device
column location for the burst access (BA0, BA1; A0–A9 for 128MB and 256MB, or A0–A9,
A11 for 512MB).
DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4,
or 8 locations. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent
operation, thereby providing high effective bandwidth by hiding row precharge and acti-
vation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All
inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class
II compatible. For more information regarding DDR SDRAM operation, refer to the
128Mb, 256Mb, or 512Mb DDR SDRAM component data sheets.
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of stor-
age are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004, 2005 Micron Technology, Inc. All rights reserved.
General Description
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