MT8VDDT6432UY-5K1 Micron Technology Inc, MT8VDDT6432UY-5K1 Datasheet - Page 16

• Manufacturer Part Number: MT8VDDT6432UY-5K1
• Description: MODULE DDR 256MB 100-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6432UY-5K1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 100-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Table 7:
Table 8:
pdf: 09005aef80745603, source: 09005aef807455eb
DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN
Name (Function)
Name (Function)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or
reserved
DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
Notes: 1. DESELECT and NOP are functionally interchangeable.
Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a gen-
eral reference of available commands. For a more detailed description of commands and
operations, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component data sheet.
2. BA0–BA1 provide device bank address and A0-A11 (128MB) or A0–A12 (256MB, 512MB)
3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB)
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
provide row address.
provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),
and A10 LOW disables the auto precharge feature.
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
banks are precharged and BA0–BA1 are “Don’t Care.”
except for CKE.
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-
tions of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide the
op-code to be written to the selected mode register.
128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM
16
CS#
H
L
L
L
L
L
L
L
L
RAS#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
CAS# WE#
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
Bank/Row
Address
Bank/Col
Bank/Col
Op-Code
©2004, 2005 Micron Technology, Inc. All rights reserved.
Code
X
X
X
X
DM
H
L
Commands
Notes
6, 7
1
1
2
3
3
4
5
8
Valid
DQs
X