MT8VDDT6432UY-5K1 Micron Technology Inc, MT8VDDT6432UY-5K1 Datasheet - Page 23

• Manufacturer Part Number: MT8VDDT6432UY-5K1
• Description: MODULE DDR 256MB 100-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6432UY-5K1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 100-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes
pdf: 09005aef80745603, source: 09005aef807455eb
DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN
10. I
11. This parameter is sampled. V
12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be
13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
14. Inputs are not recognized as valid until V
15. The output timing reference level, as measured at the timing reference point indi-
1. All voltages referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e.,
6. V
7. V
8. I
9. Enables on-chip refresh and address counters.
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
ment, but input timing is still referenced to V
and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the
device is 1V/ns in the range between V
the receiver will effectively switch as a result of the signal crossing the AC input level,
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
the DC level of the same. Peak-to-peak noise (non-common mode) on V
exceed ±2 percent of the DC value. Thus, from V
error and an additional ±25mV for AC noise. This measurement is to be taken at the
nearest V
resistors, is expected to be set equal to V
of V
with minimum cycle time at CL = 2 for -75Z and CL = 2.5 for -6 and -75 with the out-
puts open.
the defined cycle rate.
V
reflecting the fact that they are matched in loading.
derated:
500mV/ns, while
uncertain. For -6, slew rates must be ≥ 0.5 V/ns.
which CK and CK# cross; the input reference level for signals other than CK/CK# is
V
before V
cated in Note 3, is V
DD
DD
REF
OUT
REF
TT
REF
specifications are tested after the device is properly initialized, and is averaged at
is not applied directly to the device. V
is dependent on output loading and cycle rates. Specified values are obtained
.
is expected to equal V
(DC) = V
.
REF
t
REF
IS has an additional 50ps per each 100 mV/ns reduction in slew rate from
stabilizes, CKE ≤ 0.3 x
bypass capacitor.
DD
128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM
DD
Output
(V
/2, V
t
IH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is
OUT
tests may use a V
TT
DD
)
.
OUT
, and electrical AC and DC characteristics may be conducted
V
(peak to peak) = 0.2V. DM input is grouped with I/O pins,
23
SS
TT
DD
50
30pF
.
Reference
Point
DD
/2 of the transmitting device and to track variations in
Ω
= +2.5V ±0.2V, V
V
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
is recognized as LOW.
-to-V
IL
REF
(AC) and V
REF
TT
IH
and must track variations in the DC level
REF
is a system supply for signal termination
stabilizes. Exception: during the period
swing of up to 1.5V in the test environ-
(or to the crossing point for CK/CK#),
DD
REF
IH
/2, V
= VSS, f = 100 MHz, T
(AC).
©2004, 2005 Micron Technology, Inc. All rights reserved.
REF
is allowed ±25mV for DC
REF
A
may not
Notes
= 25°C,