20-101-0303 Rabbit Semiconductor, 20-101-0303 Datasheet - Page 102

• Manufacturer Part Number: 20-101-0303
• Description: SMARTSCREEN OP7100 W/TOUCHSCREEN
• Manufacturer: Rabbit Semiconductor

Specifications of 20-101-0303

• Display Type: STN - Super-Twisted Nematic
• Viewing Area: 121.00mm L x 91.00mm W
• Backlight: CCFL - White
• Dot Pitch: 0.36mm x 0.36mm
• Dot Pixels: 320 x 240 (QVGA)
• Interface: Serial
• Product: Prototyping Accessories
• Processor Type: Z180
• Sram: 128 KB
• Flash: 512 KB
• Number Of I/os: 16
• Backup Battery: 3 V Lithium Coin Type
• Operating Voltage: 10 V to 30 V
• Power Consumption: 4.5 W
• Interface Type: Ethernet
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Display Mode: -
• Dot Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 20-101-0303; 20-101-303; 20-101-303; 316-1175

Memory Map
Input/Output Select Map
The Dynamic C library functions
library allow bits in the I/O registers to be tested, set, and cleared. Both
16-bit and 8-bit I/O addresses can be used.
Z180 Internal Input/Output Registers Addresses 00-3F
The internal registers for the I/O devices built into to the Z180 processor
occupy the first 40 (hex) addresses of the I/O space. These addresses are
listed in Table C-2.
102
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11–0x13
0x14
0x15
0x16
0x17
Address
Memory, I/O Map, and Interrupt Vectors
Table C-2. Z180 Internal I/O Registers Addresses 0x00–0x3F
CNTLA0
CNTLA1
CNTLB0
CNTLB1
STAT0
STAT1
TDR0
TDR1
RDR0
RDR1
CNTR
TRDR
TMDR0L
TMDR0H
RLDR0L
RLDR0H
TCR
—
TMDR1L
TMDR1H
RLDR1L
RLDR1H
Name
Serial Channel 0, Control Register A
Serial Channel 1, Control Register A
Serial Channel 0, Control Register B
Serial Channel 1, Control Register B
Serial Channel 0, Status Register
Serial Channel 1, Status Register
Serial Channel 0, Transmit Data Register
Serial Channel 1, Transmit Data Register
Serial Channel 0, Receive Data Register
Serial Channel 1, Receive Data Register
Clocked Serial Control Register
Clocked Serial Data Register
Timer Data Register Channel 0, least
Timer Data Register Channel 0, most
Timer Reload Register Channel 0, least
Timer Reload Register Channel 0, most
Timer Control Register
Reserved
Timer Data Register Channel 1, least
Timer Data Register Channel 1, most
Timer Reload Register Channel 1, least
Timer Reload Register Channel 1, most
IBIT
,
ISET
, and
Description
IRES
in the
continued…
BIOS.LIB
OP7100