20-101-0303 Rabbit Semiconductor, 20-101-0303 Datasheet - Page 47

• Manufacturer Part Number: 20-101-0303
• Description: SMARTSCREEN OP7100 W/TOUCHSCREEN
• Manufacturer: Rabbit Semiconductor

Specifications of 20-101-0303

• Display Type: STN - Super-Twisted Nematic
• Viewing Area: 121.00mm L x 91.00mm W
• Backlight: CCFL - White
• Dot Pitch: 0.36mm x 0.36mm
• Dot Pixels: 320 x 240 (QVGA)
• Interface: Serial
• Product: Prototyping Accessories
• Processor Type: Z180
• Sram: 128 KB
• Flash: 512 KB
• Number Of I/os: 16
• Backup Battery: 3 V Lithium Coin Type
• Operating Voltage: 10 V to 30 V
• Power Consumption: 4.5 W
• Interface Type: Ethernet
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Display Mode: -
• Dot Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 20-101-0303; 20-101-303; 20-101-303; 316-1175

ASCI Control Register A
Control Register A affects various aspects of the asynchronous channel
operation.
MOD0–MOD2 (Data Format Mode Bits)
MOD0 controls stop bits: 0 ⇒ 1 stop bit, 1 ⇒ 2 stop bits. If 2 stop bits are
expected, then 2 stop bits must be supplied.
MOD1 controls parity: 0 ⇒ parity disabled, 1 ⇒ parity enabled. (See PEO
in ASCI Control Register B for even/odd parity control.)
MOD2 controls data bits: 0 ⇒ 7 data bits, 1 ⇒ 8 data bits.
MPBR/EFR (Multiprocessor Bit Receive/Error Flag Reset)
Reads and writes on this bit are unrelated. Storing a byte when this bit is 0
clears all the error flags (OVRN, FE, PE). Reading this bit obtains the
value of the MPB bit for the last read operation when the multiprocessor
mode is enabled.
/RTS0 (Request to Send, Channel 0)
Store a 1 in this bit to set the RTS0 line from the Z180 high. This bit is
essentially a 1-bit output port without other side effects.
CKA1D (CKA1 Disable)
This bit controls the function assigned to the multiplexed pin (CKA1/
~TEND0): 1 ⇒ ~TEND0 (a DMA function) and 0 ⇒ CKA1 (external
clock I/O for Channel 1 serial port).
TE (Transmitter Enable)
This bit controls the transmitter: 1 ⇒ transmitter enabled, 0 ⇒ transmitter
disabled. When this bit is cleared, the processor aborts the operation in
progress, but does not disturb TDR or TDRE.
OP7100
CNTLA0
CNTLA1
MPE
MPE
R / W
R / W
7
7
(00H)
(01H)
R / W
R / W
RE
RE
6
6
R / W
R / W
TE
TE
5
5
CKA1D
/RTS0
R / W
R / W
4
4
MPBR/
MPBR/
EFR
EFR
R / W
R / W
3
3
MOD2
MOD2
R / W
R / W
2
2
MOD1
MOD1
R / W
R / W
1
1
Hardware 47
MOD0
MOD0
R / W
R / W
0
0