ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 26

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the processor is
accessing external memory space.
Table 22. 8-Bit Memory Write Cycle
1
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
F = 7 × t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
ALEW
ADAS
ALERW
RWALE
WRH
ADAH
WW
ADWL
ADWH
DWS
DWH
DAWH
PCLK
1
1
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be 9 × t
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to Next WR Falling Edge
AD15–0 Address Hold After ALE Deasserted
WR Pulse Width
AD15–8 Address to WR Low
AD15–8 Address Hold After WR High
AD7–0 Data Setup Before WR High
AD7–0 Data Hold After WR High
AD15–8 Address to WR High
AD15
AD7
ALE
-
-
0
8
NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE
SHOWS ONLY TWO MEMORY WRITES TO PROVIDE THE NECESSARY TIMING INFORMATION.
t
ALEW
t
ADAS
Figure 19. Write Cycle for 8-Bit Memory Timing
ADDRESS
ADDRESS
VALID
VALID
Rev. G | Page 26 of 56 | March 2011
t
t
ADAH
ADWL
t
ALERW
VALID ADDRESS
PCLK
VALID DATA
t
t
.
DAWH
DWS
t
WW
Min
2 × t
t
2 × t
H + 0.5
F + H + t
t
D – F – 2.0
t
H
D – F + t
H
D – F + t
PCLK
PCLK
PCLK
t
WRH
K and B Grade
PCLK
PCLK
PCLK
– 2.8
– 0.5
– 2.8
.
VALID ADDRESS
PCLK
PCLK
PCLK
– 2.0
– 3.8
t
t
ADWH
DWH
VALID DATA
– 4.0
– 4.0
– 2.3
t
RWALE
Min
2 × t
t
2 × t
H + 0.5
F + H + t
t
D – F – 2.0
t
H
D – F + t
H
D – F + t
PCLK
PCLK
PCLK
PCLK
PCLK
– 2.8
– 0.5
– 3.5
Y Grade
PCLK
PCLK
PCLK
– 2.0
– 3.8
– 4.0
– 4.0
– 2.3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns