ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 34

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Pulse-Width Modulation Generators
Table 30. PWM Timing
1
Sample Rate Converter—Serial Input Port
The SRC input signals are routed from the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided in
Table 31
available on the ADSP-21363 models.
Table 31. SRC, Serial Input Port
1
Parameter
Switching Characteristics
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins).
The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via the PCGs or SPORTs. The PCG’s
PWMW
PWMP
SRCSFS
SRCHFS
SRCSD
SRCHD
SRCCLKW
SRCCLK
input can be either CLKIN or any of the DAI pins.
1
1
1
1
are valid at the DAI_P20–1 pins. This feature is not
OUTPUTS
PWM
PWM Output Pulse Width
PWM Output Period
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
SDATA Setup Before Serial Clock Rising Edge
SDATA Hold After Serial Clock Rising Edge
Clock Width
Clock Period
1
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SDATA)
(SCLK)
(FS)
t
PWMW
Rev. G | Page 34 of 56 | March 2011
Figure 27. SRC Serial Input Port Timing
Figure 26. PWM Timing
t
SRCCLKW
t
SRCSD
t
SRCSFS
t
PWMP
SAMPLE EDGE
Min
t
2 × t
PCLK
PCLK
– 2
– 1.5
t
t
SRCHFS
SRCHD
t
SRCCLK
Max
(2
(2
16
16
– 2) × t
– 1) × t
Min
3
3
3
3
36
80
PCLK
PCLK
– 2
Unit
ns
ns
Unit
ns
ns
ns
ns
ns
ns