ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 30

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 26. Serial Ports—External Late Frame Sync
1
Parameter
Switching Characteristics
t
t
The t
DDTLFSE
DDTENFS
DDTLFSE
1
1
and t
DDTENFS
Data Delay from Late External Transmit Frame Sync
or External Receive FS with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
NOTES: THIS FIGURE REFLECTS CHANGES MADE TO SUPPORT LEFT-JUSTIFIED SAMPLE PAIR MODE. SERIAL PORT SIGNALS
(DATA CHANNEL
(DATA CHANNEL
(FRAME SYNC)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
parameters apply to left-justified sample pair as well as serial mode, and MCE = 1, MFD = 0.
(SCLK)
(SCLK)
A/B)
A/B)
(SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS USING THE SRU. THE TIMING SPECIFICATIONS
PROVIDED ARE VALID AT THE DAI_P20–1 PINS. THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN
INTERNAL CLOCKS AND FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU.
DRIVE
DRIVE
t
t
DDTLFSE
DDTLFSE
t
t
DDTENFS
DDTENFS
t
t
SFSE/I
SFSE/I
Rev. G | Page 30 of 56 | March 2011
Figure 22. External Late Frame Sync
SAMPLE
SAMPLE
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
t
t
HFSE/I
HFSE/I
1ST BIT
1ST BIT
LATE EXTERNAL TRANSMIT FS
DRIVE
DRIVE
Min
0.5
t
t
HDTE/I
HDTE/I
K and B Grade
t
t
Max
9
DDTE/I
DDTE/I
2ND BIT
2ND BIT
Max
10.5
Y Grade
Unit
ns
ns