TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 118
TMP86C909XB
Manufacturer Part Number
TMP86C909XB
Description
EMULATION CHIP FOR TMP86F SDIP
Manufacturer
Toshiba
Datasheet
1.TMP86C909XB.pdf
(201 pages)
Specifications of TMP86C909XB
Accessory Type
Adapter
For Use With/related Products
TMP86F SDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.4 Transfer Rate
10.5 Data Sampling Method
RXD pin
RXD pin
RT clock
Internal receive data
RT clock
Internal receive data
rate are determined as follows:
detected in RXD pin input. RT clock starts detecting “L” level of the RXD pin. Once a start bit is detected, the start
bit, data bits, stop bit(s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver clock
interval (RT clock). (RT0 is the position where the bit supposedly starts.) Bit is determined according to majority
rule (The data are the same twice or more out of three samplings).
The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows.
When TC3 is used as the UART transfer rate (when UARTCR1<BRG> = “110”), the transfer clock and transfer
Transfer clock [Hz] = TC3 source clock [Hz] / TTREG3 setting value
Transfer Rate [baud] = Transfer clock [Hz] / 16
The UART receiver keeps sampling input using the clock selected by UARTCR1<BRG> until a start bit is
Table 10-1 Transfer Rate (Example)
BRG
000
001
010
100
101
011
RT0 1
RT0 1
Figure 10-4 Data Sampling Method
76800 [baud]
Start bit
Start bit
Start bit
Start bit
16 MHz
38400
19200
9600
4800
2400
2
2
3 4
3 4
5 6
5 6
(a) Without noise rejection circuit
(b) With noise rejection circuit
Page 107
7
7
8 9 10 11 12 13 14 15 0
8 9 10 11 12 13 14 15 0
38400 [baud]
Source Clock
8 MHz
19200
9600
4800
2400
1200
Bit 0
Bit 0
Bit 0
Bit 0
1
1
2 3
2 3
19200 [baud]
4 MHz
9600
4800
2400
1200
600
4 5
4 5
6
6
7 8
7 8
TMP86F409NG
9 10 11
9 10 11
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