TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 129

• Manufacturer Part Number: TMP86C909XB
• Description: EMULATION CHIP FOR TMP86F SDIP
• Manufacturer: Toshiba

Specifications of TMP86C909XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5 SEI Transfer Formats
11.5 SEI Transfer Formats
11.5.1 CPHA (SECR register bit 2) = 0 format
11.5.2 CPHA = 1 format
be selected between two.
The transfer formats are set using CPHA and CPOL (SECR<CPHA,CPOL>). CPHA allows transfer protocols to
Figure 11-2 shows a transfer format where CPHA = 0.
Note:In slave mode, be careful not to write data while the SEF flag is set and the
Figure 11-3 shows a transfer format where CPHA = 1.
Table 11-4 Transfer Format Details where CPHA = 0
SCLK cycle
SCLK
(CPOL = 0)
SCLK
(CPOL = 1)
MOSI
MISO
SECR<SEE>
SS
SEF
• In master mode, transfer is initiated by writing new data to the SEDR register. At this time, the new
• In slave mode, writing data to the SEDR register is inhibited when the
CPOL = 0
CPOL = 1
data changes state on the MOSI pin a half clock period before the shift clock starts pulsing. Use BOS
(SECR<BOS>) to select whether the data should be shifted out beginning with the MSB or LSB. The
SEF flag (SESR<SEF>) is set after the last shift cycle.
this period causes collision of writes, so that the WCOL flag (SESR<WCOL>) is set.
Therefore, when writing data to the SEDR (SEI Data Register) after the SEF flag is set upon comple-
tion of transfer, make sure the
Internal
shift clock
Figure 11-2 Transfer Format where CPHA = 0
Communicating (IDLE)
SCLK Level when not
“H” level
“L” level
1
2
SS
Falling edge of transfer clock
Rising edge of transfer clock
pin goes “H” again before writing the next data to the SEDR register.
3
Page 118
Data Shift
4
5
6
Rising edge of transfer clock
Falling edge of transfer clock
7
SS
Data Sampling
pin remains “L”.
SS
8
pin is “L”. A write during
TMP86F409NG