TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 31
TMP86C909XB
Manufacturer Part Number
TMP86C909XB
Description
EMULATION CHIP FOR TMP86F SDIP
Manufacturer
Toshiba
Datasheet
1.TMP86C909XB.pdf
(201 pages)
Specifications of TMP86C909XB
Accessory Type
Adapter
For Use With/related Products
TMP86F SDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 31 of 201
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2.2 System Clock Controller
2.2.4.2
interrupts. The following status is maintained during these modes.
IDLE1/2 mode and SLEEP1/2 mode
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable
1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to
2. The data memory, CPU registers, program status word and port output latches are all held in the
3. The program counter holds the address 2 ahead of the instruction which starts these modes.
operate.
status in effect before these modes were entered.
Figure 2-10 IDLE1/2 and SLEEP1/2 Modes
release mode
Normal
“0”
No
Execution of the instruc-
IDLE1/2 and SLEEP1/2
modes start instruction
CPU and WDT are halted
tion which follows the
Starting IDLE1/2 and
SLEEP1/2 modes by
Interrupt processing
Interrupt request
Page 20
Reset input
instruction
IMF
Yes
No
“1” (Interrupt release mode)
Yes
Reset
TMP86F409NG
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