MCP1631RD-MCC2 Microchip Technology, MCP1631RD-MCC2 Datasheet - Page 237
![REFERENCE DESIGN MCP1631HV](/photos/9/4/90424/mcp1631rd-mcc2_sml.jpg)
MCP1631RD-MCC2
Manufacturer Part Number
MCP1631RD-MCC2
Description
REFERENCE DESIGN MCP1631HV
Manufacturer
Microchip Technology
Datasheets
1.MCP1631VHVT-330EST.pdf
(34 pages)
2.MCP1631HV-330EST.pdf
(54 pages)
3.MCP1631RD-MCC2.pdf
(20 pages)
4.MCP1631RD-MCC2.pdf
(328 pages)
Specifications of MCP1631RD-MCC2
Main Purpose
Power Management, Battery Charger
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
MCP1631HV, PIC16F883
Primary Attributes
1 ~ 2 Cell- Li-Ion, 1 ~ 5 Cell- NiCd/NiMH, 1 ~ 2 1W LEDs
Secondary Attributes
Status LEDs
Silicon Manufacturer
Microchip
Application Sub Type
Battery Charger
Kit Application Type
Power Management - Battery
Silicon Core Number
MCP1631HV, PIC16F883
Kit Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCP1631VHVT-330EST PDF datasheet
- MCP1631HV-330EST PDF datasheet #2
- MCP1631RD-MCC2 PDF datasheet #3
- MCP1631RD-MCC2 PDF datasheet #4
- Current page: 237 of 328
- Download datasheet (6Mb)
DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Description:
INCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
© 2009 Microchip Technology Inc.
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
d ∈ [0,1]
(f) - 1 → (destination);
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, then a NOP is
executed instead, making it a
two-cycle instruction.
Unconditional Branch
[ label ]
0 ≤ k ≤ 2047
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
None
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
Increment f
[ label ]
0 ≤ f ≤ 127
d ∈ [0,1]
(f) + 1 → (destination)
Z
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
GOTO k
INCF f,d
PIC16F882/883/884/886/887
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Increment f, Skip if 0
[ label ]
0 ≤ f ≤ 127
d ∈ [0,1]
(f) + 1 → (destination),
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOP is executed
instead, making it a two-cycle
instruction.
Inclusive OR W with f
[ label ]
0 ≤ f ≤ 127
d ∈ [0,1]
(W) .OR. (f) → (destination)
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
skip if result = 0
Inclusive OR literal with W
[ label ]
0 ≤ k ≤ 255
(W) .OR. k → (W)
Z
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
INCFSZ f,d
IORWF
IORLW k
DS41291F-page 235
f,d
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