STEVAL-IPE009V1 STMicroelectronics, STEVAL-IPE009V1 Datasheet - Page 33

• Manufacturer Part Number: STEVAL-IPE009V1
• Description: BOARD EVAL ST72321BR9/STPM14
• Manufacturer: STMicroelectronics
• Type: Other Power Managementr

Specifications of STEVAL-IPE009V1

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: STPM14, ST72F321BR9T6
• Primary Attributes: 1-Ph 220 VAC, LCD Displays: No-Load, Reverse, Fraud, or Case Tampering
• Secondary Attributes: Up to 4 Tariff Rates, Data Accumulated for Meter Life, Time Stamp for: Tamper, Fraud, Power Failure
• Input Voltage: 220 V
• Product: Power Management Modules
• Silicon Manufacturer: ST Micro
• Silicon Core Number: ST72321BR9 And STPM14
• Features: Continuously Detects, Displays No-Load Condition, Reverse Direction, Fraud And Case Tamper Condition
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: STPM14, ST72321BR9
• Other names: 497-8434; STEVAL-IPE009V1

STPM11, STPM12, STPM13, STPM14
Permanent writing of the CFG bits
In order to make a permanent set of some CFG bits, use the following procedure:
For steps of set or clear, apply the timing shown in
SDA-TD.
In order to create a permanent set of the TSTD bit, which does not result in any more writing
to the Configuration bits, the procedure above must be conducted in such a way that steps 6
to 13 are performed in series during a single period of active SCS. The idle state of SCS
would make the signal TSTD immediately effective which in turn, would abort the procedure
and possibly destroy the device due to clearing of system signal RD. This would result in the
connecting of all gates of 3 V NMOS sense amplifiers of already permanently set CFG bits
to the V
1. collect all addresses of CFG bits to be permanently set into a list;
2. clear all OTP shadow latches;
3. set the system signal RD;
4. connect a current source of at least +14 V, 1 mA to 3 mA to VOTP;
5. wait for VOTP voltage to be stable;
6. set one OTP shadow latch from the list;
7. set the system signal WE;
8. wait for 300 s;
9. clear the system signal WE;
10. clear the OTP shadow latch which was set in step 6;
11. until all CFG bits are permanently set as desired, repeat steps 5 to 11;
12. disconnect the current source;
13. wait for VOTP voltage to be less than 3 V;
14. clear the system signal RD;
15. verify the correct writing, testing STPM1x operation;
16. if the verification of CFG bits fails, repeat steps 1 to 16.
OTP
source.
Doc ID 13167 Rev 7
Figure 21
- with proper signal on the
Theory of operation
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