DC-VIDEO-TVP5146N Altera, DC-VIDEO-TVP5146N Datasheet - Page 55

• Manufacturer Part Number: DC-VIDEO-TVP5146N
• Description: VIDEO DAUGHTER CARD
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of DC-VIDEO-TVP5146N

• Main Purpose: Video, Daughter Card
• Embedded: No
• Utilized Ic / Part: Altera Dev Kits
• Primary Attributes: Dual Composite Video Input - NTSC or PAL
• Secondary Attributes: 10-bit BT.656 Output, Compatible with Expansion Connector, Standard on Most Altera Development Kits
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1704

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–45. EP3SL50 Column Pins Input Timing Parameters (Part 1 of 2)
© July 2010 Altera Corporation
LVDS
MINI-LVDS
RSDS
DIFFERENTIAL
1.2-V HSTL
CLASS I
DIFFERENTIAL
1.2-V HSTL
CLASS II
DIFFERENTIAL
1.5-V HSTL
CLASS I
DIFFERENTIAL
1.5-V HSTL
CLASS II
DIFFERENTIAL
1.8-V HSTL
CLASS I
I/O Standard
Clock
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Table 1–45
devices for differential I/O standards.
Table 1–45
standards.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
su
su
su
su
su
su
su
su
su
su
su
su
su
su
su
su
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
Industrial
-0.697
-0.892
-0.697
-0.892
-0.705
-0.884
-0.705
-0.884
-0.717
-0.872
-0.717
-0.872
-0.705
-0.884
-0.705
-0.884
0.814
1.143
0.814
1.143
0.822
1.135
0.822
1.135
0.834
1.123
0.834
1.123
0.822
1.135
0.822
1.135
Fast Model
through
lists the EP3SL50 column pins input timing parameters for differential I/O
Commercial
-0.717
-0.893
-0.717
-0.893
-0.729
-0.881
-0.729
-0.881
-0.740
-0.870
-0.740
-0.870
-0.729
-0.881
-0.729
-0.881
0.849
1.159
0.849
1.159
0.861
1.147
0.861
1.147
0.872
1.136
0.872
1.136
0.861
1.147
0.861
1.147
Table 1–48
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727
1.257
1.821
1.257
1.821
1.267
1.811
1.267
1.811
1.277
1.802
1.277
1.802
1.267
1.811
1.267
1.811
1.1 V
V
C2
CCL
list the maximum I/O timing parameters for EP3SL50
=
1.389
2.053
1.389
2.053
1.400
2.042
1.400
2.042
1.411
2.031
1.411
2.031
1.400
2.042
1.400
2.042
1.1 V
V
C3
CCL
=
1.522
2.279
1.522
2.279
1.538
2.263
1.538
2.263
1.557
2.244
1.557
2.244
1.538
2.263
1.538
2.263
1.1 V
V
C4
CCL
=
1.454
2.166
1.454
2.166
1.470
2.150
1.470
2.150
1.489
2.131
1.489
2.131
1.470
2.150
1.470
2.150
1.1 V
V
CCL
=
C4L
1.740
2.172
1.740
2.172
1.756
2.156
1.756
2.156
1.775
2.137
1.775
2.137
1.756
2.156
1.756
2.156
0.9 V
V
Stratix III Device Handbook, Volume 2
CCL
=
1.398
2.063
1.398
2.063
1.409
2.052
1.409
2.052
1.420
2.041
1.420
2.041
1.409
2.052
1.409
2.052
1.1 V
V
I3
CCL
=
1.532
2.288
1.532
2.288
1.547
2.273
1.547
2.273
1.565
2.255
1.565
2.255
1.547
2.273
1.547
2.273
1.1 V
V
I4
CCL
=
1.469
2.173
1.469
2.173
1.484
2.158
1.484
2.158
1.502
2.140
1.502
2.140
1.484
2.158
1.484
2.158
1.1 V
V
CCL
1–55
=
I4L
1.777
2.219
1.777
2.219
1.792
2.204
1.792
2.204
1.810
2.186
1.810
2.186
1.792
2.204
1.792
2.204
0.9 V
V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns