DAC1405D750/DB,598 NXP Semiconductors, DAC1405D750/DB,598 Datasheet - Page 39

BOARD DEMO FOR DAC1405D750

DAC1405D750/DB,598

Manufacturer Part Number
DAC1405D750/DB,598
Description
BOARD DEMO FOR DAC1405D750
Manufacturer
NXP Semiconductors
Type
D/Ar

Specifications of DAC1405D750/DB,598

Number Of Dac's
2
Number Of Bits
14
Outputs And Type
2, Differential
Sampling Rate (per Second)
750M
Data Interface
Serial, SPI™
Settling Time
20ns
Dac Type
Current
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
DAC1405D750
Product
Data Conversion Development Tools
Conversion Rate
750 MSPS
Resolution
14 bit
Interface Type
SMA
Supply Voltage (max)
3.3 V
Supply Voltage (min)
1.8 V
For Use With/related Products
DAC1405D750
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-5090
NXP Semiconductors
13. Glossary
14. Revision history
Table 44.
DAC1405D750
Product data sheet
Document ID
DAC1405D750 v.3
Modifications:
DAC1405D750 v.2
Modifications:
DAC1405D750 v.1
Revision history
Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the
reconstructed output sine wave and the RMS value of the largest spurious observed
(harmonic and non-harmonic, excluding DC component) in the frequency domain.
Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these
two frequencies being close together), the intermodulation distortion products IMD2 and
IMD3 (respectively, second and third-order components) are defined below.
IMD2 — The ratio of the RMS value of either tone to the RMS value of the worst second
order intermodulation product.
IMD3 — The ratio of the RMS value of either tone to the RMS value of the worst third
order intermodulation product.
Restricted Bandwidth Spurious Free Dynamic Range — The ratio of the RMS value of
the reconstructed output sine wave to the RMS value of the noise, including the
harmonics, in a given bandwidth centered around f
Release date
20100907
20100727
20100310
Figure
Figure 1: changed pins I14 to I13 and Q14 to Q13
Table 5: updated some typ. and max. values
Table 38: changed data 0 two’s complement value
All information provided in this document is subject to legal disclaimers.
18:corrected the value of the resistors on pin AUXnP
Rev. 3 — 7 September 2010
Data sheet status
Product data sheet
Product data sheet
Preliminary data sheet
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
offset
Change notice
-
-
-
.
DAC1405D750
DAC1405D750 v.2
DAC1405D750 v.1
-
Supersedes
© NXP B.V. 2010. All rights reserved.
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