XE8000EV110 Semtech, XE8000EV110 Datasheet - Page 165

• Manufacturer Part Number: XE8000EV110
• Description: EVAL BOARD FOR XE8802AMI035LF
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV110

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC02MI035
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

19.6 Parallel I/O port capabilities
19.6.1
All pins pad_lcd_io[31:0] can be used as a general input/output digital port. The peripheral is set to this mode by
writing all bits of the register RegLcdSe to ‘0’. Figure 19-16 shows the structure for one pin and the registers used
in this mode. Since the peripheral has 32 pins, 4 of each of the registers in Figure 19-16 exist. They are labelled
with the suffix 0 to 3. The mapping of the register bits to the I/O pins is given in Table 19-26. As an example, the bit
PLcdPullup2[6] in RegPLcdPullup2 controls the pull up resistor of the pin pad_lcd_io[22].
The direction of each pin pad_lcd_io[31:0] (input or output) can be individually set by using the RegPLcdDirN
registers. If PLcdDirN[n] = 1, the output buffer of the corresponding pad_lcd_io[8N+n] is enabled.
Output mode:
The data to be output is stored in RegPLcdOutN. In output mode, the pull-up resistors should be switched off by
writing ‘0’ to the registers RegPLcdPullupN. If not, current will flow through the pull-up resistors when the output is
forced to ‘0’.
© Semtech 2006
Figure 19-15. Generation of LCD voltages with external resistors ladder in 1/3 (a) and 1/2 (b) bias
Parallel port function
VgenOff = 1
VgenRefEn = 0
VGEN
1.2V voltage
suffix of the register
reference
(a)
0≤N≤3
N
LCD driver
Table 19-26. Register bit to pin mapping
pad_v gen_v 2
pad_v gen_v 1
pad_v gen_v 3
pad_v gen_v a
pad_gen_v b
XE8802 Sensing Machine Data Acquisition MCU
bit in the register
Vext
R
R
R
0≤n≤7
19-21
3
2
1
n
mode.
with ZoomingADC™ and LCD driver
VgenOff = 1
VgenRefEn = 0
VGEN
1.2V voltage
reference
pad_lcd_io[8N+n]
(b)
pin
LCD driver
pad_v gen_v 2
pad_v gen_v 1
pad_v gen_v 3
pad_v gen_v a
pad_gen_v b
Vext
www.semtech.com
R
R
3
1