XE8000EV110 Semtech, XE8000EV110 Datasheet - Page 179

• Manufacturer Part Number: XE8000EV110
• Description: EVAL BOARD FOR XE8802AMI035LF
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV110

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC02MI035
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CntDDownUp). The mapping of the interrupt sources IrqC and IrqD and the PWM output on PB(1) in these
different modes is also shown.
The switching between different modes must be done while the concerned counters are stopped. While switching
capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode
change.
20.9 Counter / Timer mode
The counters in counter / timer mode are generally used to generate interrupts after a predefined number of clock
periods applied on the counter clock input.
Each counter can be set individually either in upcount mode by setting CntXDownUp in the register
RegCntConfig1 or in downcount mode by resetting this bit. Counters A and B can be cascaded to behave as a 16
bit counter by setting CascadeAB in the RegCntConfig1 register. Counters C and D can be cascaded by setting
CascadeCD. When cascaded, the up/down count modes of the counters B and D are defined respectively by the
up/down count modes set for the counters A and C.
When in upcount mode, the counter will start incrementing from zero up to the target value which has been written
in the corresponding RegCntX register(s). When the counter content is equal to the target value, an interrupt is
generated at the next counter clock pulse and the counter is loaded again with the zero value (Figure 20-2).
When in downcount mode, the counter will start decrementing from the initial load value which has been written in
the corresponding RegCntX register(s) down to the zero value. Once the counter content is equal to zero, an
interrupt is generated at the next counter clock pulse and the counter is loaded again with the load value (Figure
20-2).
Be careful to select the counter mode (no capture, not PWM, specify cascaded or not and up or down counting
mode) before writing any target or load value to the RegCntX register(s). This ensures that the counter will start
from the correct initial value. When counters are cascaded, both counter registers must be written to ensure that
both cascaded counters will start from the correct initial values.
The stopping and consecutive starting of a counter in counter mode without a target or load value write operation in
between can generate an interrupt if this counter has been stopped at the zero value (downcount) or at it’s target
value (upcount). This interrupt is additional to the interrupt which has already been generated when the counter
reached the zero or the target value.
Due to the synchronization between the CPU clock and the counter clock source, it may take up to 1 CPU clock
cycle before the configuration changes written in the RegCntConfigX or RegCntX registers are becoming
effective. In order to get correct operation of the counters, there should be at least 1 software instruction between
the modification of RegCntConfigX or RegCntX and the enabling of the counters.
© Semtech 2006
CascadeCD
0
1
0
1
CountPWM1
Table 20-13: Operating modes of the counters C and D
0
0
1
1
XE8802 Sensing Machine Data Acquisition MCU
Counter 8b
Downup: C
Downup: C
Counter C
PWM 8b
mode
PWM 10 – 16b CD
Counter 16b CD
Downup: C
Downup: C
20-7
Counter 8b
Downup: D
Counter 8b
Downup: D
Counter D
with ZoomingADC™ and LCD driver
mode
Counter
Counter
source
IrqC
CD
C
-
-
Counter
Counter
source
IrqD
D
D
-
-
PWM CD
function
PWM C
PB(1)
PB(1)
PB(1)
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