XE8000EV110 Semtech, XE8000EV110 Datasheet - Page 166

• Manufacturer Part Number: XE8000EV110
• Description: EVAL BOARD FOR XE8802AMI035LF
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV110

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC02MI035
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
PORT
R
RegPlcdPullup
RegPlcdOut
RegPlcdDir
RegPlcdIn
Figure 19-16. Structure of the LCD driver used as parallel port
Input mode:
The status of the pins pad_lcd_io is available in RegPLcdInN (read only). Reading is always direct, there is no
digital debounce function. In case of noisy input signals, a software debouncer or an external filter must be realised.
The pull-up resistors are individually controllable for each pin by setting the corresponding bit in the registers
RegPLcdPullN (1=active, 0=inactive).
19.6.2
Parallel Port Voltage
When the peripheral is used as a parallel port, the internal voltage generator is not required (VgenOff=1 and
VgenRefEn=0 in RegVgenCfg0). For normal operation as a standard parallel port, the circuit is connected as
shown in Figure 19-17. In this case, the logical ‘1’ corresponds to the voltage VBAT.
The parallel port can also be driven from another voltage than VBAT. This allows the circuit to be interfaced to
other circuits that have a different supply voltage domain VDD1 that can be either lower or higher than VBAT
without adding any extra hardware as shown in Figure 19-18.
The parallel port can be split in several voltage domains. The pins pad_lcd_io[31:12] are supplied from the
pad_vgen_v3 pin. The pins pad_lcd_io[11:4] are supplied from the pin pad_lcd_vr1 and the pins pad_lcd_io[3:0]
are supplied from the pin pad_lcd_vr2. Each of these can be supplied with a different voltage as shown in Figure
19-19. As an example, VBAT could be supplied at 2.7V, VDD1 at 2.2V, VDD2 at 3.3V and VDD3 at 5V. The only
limitation is that VDD1>VREG, VDD2>VREG, VDD3>VREG.
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