C8051F800DK Silicon Laboratories Inc, C8051F800DK Datasheet - Page 145

• Manufacturer Part Number: C8051F800DK
• Description: KIT DEV C8051F800
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F800DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F800
• Data Bus Width: 16 bit
• Interface Type: USB
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F8xx
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1797

Figure 23.5. Priority Crossbar Decoder Example 1—No Skipped Pins
In this example, the crossbar is configured to assign the UART TX0 and
RX0 signals, the SPI signals, and the PCA signals. Note that the SPI
signals are assigned as multiple signals, and there are no pins skipped
using the P0SKIP or P1SKIP registers.
in this configuration.
1
2
3
P0.3, respectively.
4
respectively.
All unassigned pins can be used as GPIO or for other non-crossbar
functions.
Notes:
1. P1.4-P1.7 are not available on 16-pin packages.
2. NSS is only pinned out when the SPI is in 4-wire mode.
Pin Number
st
nd
rd
th
TX0 is assigned to P0.4
CEX0, CEX1, and CEX2 are assigned to P0.6, P0.7, and P1.0,
SCK, MISO, MOSI, and NSS are assigned to P0.0, P0.1, P0.2, and
RX0 is assigned to P0.5
These boxes represent the port pins which are used by the peripherals
SYSCLK
Function
Pin Skip
Settings
Special
Signals
CP0A
CEX0
CEX1
CEX2
MISO
MOSI
NSS
SCK
SDA
RX0
SCL
CP0
Port
TX0
ECI
T0
T1
2
0
0
1
0
2
0
P0SKIP
3
0
P0
4
0
Rev. 1.0
5
0
6
0
7
0
0
0
1
0
2
0
P1SKIP
3
0
P1
4
0
C8051F80x-83x
1
5
0
1
6
0
1
7
0
1
0
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