C8051T606DK Silicon Laboratories Inc, C8051T606DK Datasheet - Page 124

• Manufacturer Part Number: C8051T606DK
• Description: KIT DEVELOPMENT FOR C8051T606
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051T606DK

• Contents: Board, Adapter, Cable, CD, Power Supply
• Processor To Be Evaluated: C8051T606x
• Interface Type: RS-232, USB
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T606
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1666

C8051T600/1/2/3/4/5/6
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 23.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “25. Timers” on page 145.
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 23.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 23.2.
Figure 23.4 shows the typical SCL generation described by Equation 23.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by Equation 23.1.
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
124
Timer Source
Overflows
SCL
LOW
Equation 23.1. Minimum SCL High and Low Times
T
Low
. The actual SCL output may vary due to other devices on the bus (SCL may be
Figure 23.4. Typical SMBus SCL Generation
Table 23.1. SMBus Clock Source Selection
SMBCS1
T
Equation 23.2. Typical SMBus Bit Rate
HighMin
0
0
1
1
BitRate
T
SMBCS0
=
High
T
0
1
0
1
LowMin
=
f
--------------------------------------------- -
ClockSourceOverflow
Rev. 1.2
=
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
SMBus Clock Source
--------------------------------------------- -
f
ClockSourceOverflow
Timer 0 Overflow
Timer 1 Overflow
3
1
SCL High Timeout
HIGH
is typically