C8051T606DK Silicon Laboratories Inc, C8051T606DK Datasheet - Page 174
C8051T606DK
Manufacturer Part Number
C8051T606DK
Description
KIT DEVELOPMENT FOR C8051T606
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051T600EDB.pdf
(188 pages)
2.C8051T606TDB.pdf
(1 pages)
3.C8051T606DK.pdf
(16 pages)
4.C8051T606TDB.pdf
(14 pages)
Specifications of C8051T606DK
Contents
Board, Adapter, Cable, CD, Power Supply
Processor To Be Evaluated
C8051T606x
Interface Type
RS-232, USB
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T606
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1666
- C8051T600EDB PDF datasheet
- C8051T606TDB PDF datasheet #2
- C8051T606DK PDF datasheet #3
- C8051T606TDB PDF datasheet #4
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- Download datasheet (898Kb)
C8051T600/1/2/3/4/5/6
SFR Definition 26.2. PCA0MD: PCA Mode
SFR Address = 0xD9
174
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
Name
Reset
3:1
Bit
Type
7
6
5
4
0
Bit
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
CPS[2:0] PCA Counter/Timer Pulse Select.
WDLCK
Unused
WDTE
Name
CIDL
ECF
CIDL
R/W
7
0
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Watchdog Timer Enable.
If this bit is set, PCA Module 2 is used as the Watchdog Timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
Unused. Read = 0b, Write = Don't care.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
WDTE
R/W
6
1
WDLCK
R/W
5
0
Rev. 1.2
R
4
0
Function
3
0
CPS[2:0]
R/W
2
0
1
0
ECF
R/W
0
0
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