DK-EMB-3C120N Altera, DK-EMB-3C120N Datasheet - Page 24

KIT DEV EMB CYCLONE III EDITION

DK-EMB-3C120N

Manufacturer Part Number
DK-EMB-3C120N
Description
KIT DEV EMB CYCLONE III EDITION
Manufacturer
Altera
Series
Cyclone® IIIr
Type
FPGAr

Specifications of DK-EMB-3C120N

Contents
Board, Cables, CD(s), USB-Blaster™, Power Supply
Architecture
PLD/FPGA
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Cyclone
Silicon Core Number
EP3C
Silicon Family Name
Cyclone III
Rohs Compliant
Yes
For Use With/related Products
EP3C120
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2589

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-EMB-3C120N
Manufacturer:
Altera
Quantity:
135
Part Number:
DK-EMB-3C120N
Manufacturer:
ALTERA
0
6–4
Using the Board Test System
Cyclone III FPGA Development Kit User Guide
The Configure Menu
The Config Tab
This section describes each control in the Board Test System application.
Each test design tests different functionality and corresponds to one or more
application tabs. Use the Configure menu to select the design you want to use.
Figure 6–2
Figure 6–2. The Configure Menu
1. To configure the FPGA with a test system design, perform the following steps:On
2. In the dialog box that appears, click Configure to download the corresponding
3. When configuration finishes, the design begins running in the FPGA. The
The Config tab shows information about the board’s current configuration.
Figure 6–1 on page 6–2
JTAG chain, the flash memory map, and other details stored on the board.
The following sections describe the controls on the Config tab.
MAX II Registers
The MAX II registers control allow you to view the current MAX II register values.
The values are set when you load the test system design into the FPGA and is not
configurable.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Cyclone III device is always the first device in the chain.
the Configure menu, click the configure command that corresponds to the
functionality you wish to test.
SRAM/Flash/GPIO design object file (.sof) to the FPGA. The download process
usually takes about a minute.
corresponding GUI application tab that interfaces with the design is enabled.
shows the Configure menu.
shows the Config tab. The tab displays the contents of the
September 2010 Altera Corporation
Chapter 6: Board Test System
Using the Board Test System

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