ADSP-3PARCBF548E02 Analog Devices Inc, ADSP-3PARCBF548E02 Datasheet - Page 42

• Manufacturer Part Number: ADSP-3PARCBF548E02
• Description: KIT DEV STARTER BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADSP-3PARCBF548E02

• Contents: Board, Cables, CD, Headset with Microphone, Module, Power Supply
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
TIMING SPECIFICATIONS
Timing specifications are detailed in this section.
Clock and Reset Timing
Table 25
Table 26
Table 25. Clock Input and Reset Timing
1
2
3
4
5
6
7
8
9
10
11
Parameter
Timing Requirements
t
t
t
t
t
t
t
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
Applies to PLL bypass mode and PLL non-bypass mode.
CLKIN frequency and duty cycle must not change on the fly.
If the DF bit in the PLL_CTL register is set, then the maximum t
Applies after power-up sequence is complete. See
Maximum value not specified due to variation resulting from boot mode selection and OTP memory programming.
Values specified assume no invalidation preboot settings in OTP page PBS00L. Invalidating a PBS set will increase the value by 1875 t
Applies only to boot modes BMODE=1, 2, 4, 6, 7, 10, 11, 14, 15.
Use default t
When enabled by OTP_RESETOUT_HWAIT bit. If regular HWAIT is not required in an application, the OTP_RESETOUT_HWAIT bit in the same page instructs the
Variances are mainly dominated by PLL programming instructions in PBS00L page and boot code differences between silicon revisions. The earlier is bypassed in boot mode
CKIN
CKINL
CKINH
BUFDLAY
WRST
RHWFT
RHWFT
HWAIT or HWAITA to simulate reset output functionality. Then an external resistor is expected to pull the signal to the reset level, as the pin itself is in high performance
mode during reset.
BMODE = 0. Maximum value assumes PLL programming instructions do not cause the SCLK frequency to decrease.
and
and
SCLK
Figure 10
Figure 11
value unless PLL is reprogrammed during preboot. In case of PLL reprogramming use the new t
HWAIT (A)
CLKBUF
RESET
CLKIN
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
CLKIN to CLKBUF Delay
RESET Asserted Pulsewidth Low
RESET High to First HWAIT/HWAITA Transition (Boot Host Wait Mode)
RESET High to First HWAIT/HWAITA Transition (Reset Output Mode)
describe Clock Input and Reset Timing.
describe Clock Out Timing.
1, 2, 3, 4
t
CKINL
2
2
t
CKIN
Table 27
t
CKINH
and
5
Rev. C | Page 42 of 100 | February 2010
Figure 12
CKIN
Figure 10. Clock and Reset Timing
period is 50 ns.
t
WRST
for more information about power-up reset timing.
VCO
, f
t
RHWFT
CCLK
7,10,11
t
, and f
BUFDLAY
6,7,8,9
SCLK
SCLK
Min
20.0
8.0
8.0
11 t
6100 t
6100 t
settings discussed in
value and add PLL_LOCKCNT settle time.
CKIN
CKIN
CKIN
+ 7900 t
CKIN
SCLK
Table 16
(typically).
t
BUFDLAY
Max
100.0
10
7000 t
and
Table 13 on Page
CKIN
Unit
ns
ns
ns
ns
ns
ns
ns
35.