ADSP-3PARCBF548E02 Analog Devices Inc, ADSP-3PARCBF548E02 Datasheet - Page 50
![KIT DEV STARTER BF548](/photos/9/25/92500/adsp-3parcbf548e02_kit_sml.jpg)
ADSP-3PARCBF548E02
Manufacturer Part Number
ADSP-3PARCBF548E02
Description
KIT DEV STARTER BF548
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
DSPr
Specifications of ADSP-3PARCBF548E02
Contents
Board, Cables, CD, Headset with Microphone, Module, Power Supply
For Use With/related Products
ADSP-BF548
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 50 of 100
- Download datasheet (4Mb)
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing
Table 34
SDRAM write cycle timing.
Table 34. DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
DQSS
DS
DH
DSS
DSH
DQSH
DQSL
WPRE
WPST
DOPW
and
Figure 20
Write CMD to First DQS0-1
DQ0-15/DQM0-1 Setup to DQS0-1
DQ0-15/DQM0-1 Hold to DQS0-1
DQS0-1 Falling to DCK0-1 Rising (DQS0-1 Setup)
DQS0-1 Falling from DCK0-1 Rising (DQS0-1 Hold)
DQS0-1 High Pulse Width
DQS0-1 Low Pulse Width
DQS0-1 Write Preamble
DQS0-1 Write Postamble
DQ0-15 and DQM0-1 Output Pulse Width (for Each)
DQ0-15/DQM0-1
CONTROL
DCK0-1
DQS0-1
describe DDR SDRAM/mobile DDR
Write CMD
Figure 20. DDR SDRAM /Mobile DDR SDRAM Controller Write Cycle Timing
NOTE: CONTROL = DCS0-1, DCLKE, DRAS, DCAS, AND DWE.
t
DQSS
Rev. C | Page 50 of 100 | February 2010
t
WPRE
t
DS
t
DOPW
Dn
t
DDR SDRAM
Min
0.75
0.90
0.90
0.20
0.20
0.35
0.35
0.25
0.40
1.75
DH
t
DSH
Dn+1
t
t
DSS
DQSL
Max
1.25
0.60
Dn+2
t
DQSH
Mobile DDR SDRAM
Min
0.75
0.90
0.90
0.20
0.20
0.40
0.40
0.25
0.40
1.75
Dn+3
t
WPST
Max
1.25
0.60
0.60
0.60
Unit
t
ns
ns
t
t
t
t
t
t
ns
CK
CK
CK
CK
CK
CK
CK
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