ADSP-3PARCBF548E02 Analog Devices Inc, ADSP-3PARCBF548E02 Datasheet - Page 43
![KIT DEV STARTER BF548](/photos/9/25/92500/adsp-3parcbf548e02_kit_sml.jpg)
ADSP-3PARCBF548E02
Manufacturer Part Number
ADSP-3PARCBF548E02
Description
KIT DEV STARTER BF548
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
DSPr
Specifications of ADSP-3PARCBF548E02
Contents
Board, Cables, CD, Headset with Microphone, Module, Power Supply
For Use With/related Products
ADSP-BF548
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 43 of 100
- Download datasheet (4Mb)
Table 26. Clock Out Timing
1
2
Table 27. Power-Up Reset Timing
Parameter
Timing Requirements
t
Parameter
Switching Characteristics
t
t
t
The t
The t
RST_IN_PWR
SCLK
SCLKH
SCLKL
SCLK
SCLK
value is the inverse of the f
value does not account for the effects of jitter.
V
DD_SUPPLIES
RESET Deasserted After the V
CLKIN Pins Are Stable and Within Specification
RESET
CLKIN
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
CLKOUT
SCLK
In
specification. Reduced supply voltages affect the best-case value of 7.5 ns listed here.
Figure
1,2
12, V
DDINT
, V
DD_SUPPLIES
DDEXT
Rev. C | Page 43 of 100 | February 2010
, V
Figure 11. CLKOUT Interface Timing
DDDDR
Figure 12. Power-Up Reset Timing
t
is V
RST_IN_PWR
DDINT
,V
DDUSB
, V
DDEXT
,V
t
SCLK
DDRTC
, V
DDDDR
,V
DDVR
, V
,V
DDUSB
DDMP
, V
, and
DDRTC
, V
t
SCLKL
Min
3500 × t
DDVR
, and V
t
SCLKH
CKIN
DDMP
Min
7.5
2.5
2.5
.
Max
Max
Unit
ns
Unit
ns
ns
ns
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