ADSP-3PARCBF548E02 Analog Devices Inc, ADSP-3PARCBF548E02 Datasheet - Page 53

• Manufacturer Part Number: ADSP-3PARCBF548E02
• Description: KIT DEV STARTER BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADSP-3PARCBF548E02

• Contents: Board, Cables, CD, Headset with Microphone, Module, Power Supply
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NAND Flash Controller Interface Timing
Table 37
Page 56
Table 37. NAND Flash Controller Interface Timing
1
Parameter
Write Cycle
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
Read Cycle
Switching Characteristics
t
t
t
t
t
Timing Requirements
t
t
Write Followed by Read
Switching Characteristic
t
WR_DLY and RD_DLY are defined in the NFC_CTL register.
CWL
CH
CLHWL
CLH
ALLWL
ALH
WP
WHWL
WC
DWS
DWH
CRL
CRH
RP
RHRL
RC
DRS
DRH
WHRL
1
1
1
1
1
describe NAND flash controller interface operations.
and
Figure 23 on Page 54
ND_CE Setup Time to AWE Low
ND_CE Hold Time from AWE High
ND_CLE Setup Time High to AWE Low
ND_CLE Hold Time from AWE High
ND_ALE Setup Time Low to AWE Low
ND_ALE Hold Time from AWE High
AWE Low to AWE High
AWE High to AWE Low
AWE Low to AWE Low
Data Setup Time for a Write Access
Data Hold Time for a Write Access
ND_CE Setup Time to ARE Low
ND_CE Hold Time from ARE High
ARE Low to ARE High
ARE High to ARE Low
ARE Low to ARE Low
Data Setup Time for a Read Transaction
Data Hold Time for a Read Transaction
AWE High to ARE Low
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
through
Figure 27 on
Rev. C | Page 53 of 100 | February 2010
Min
1.0 × t
3.0 × t
0.0
2.5 × t
0.0
2.5 × t
(WR_DLY +1.0) × t
4.0 × t
(WR_DLY +5.0) × t
(WR_DLY +1.5) × t
2.5 × t
1.0 × t
3.0 × t
(RD_DLY +1.0) × t
4.0 × t
(RD_DLY + 5.0) × t
8.0
0.0
5.0 × t
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
– 4
– 4
– 4
– 4
– 4
– 4
– 4
– 4
– 4
– 4
SCLK
SCLK
SCLK
SCLK
SCLK
– 4
– 4
– 4
– 4
– 4
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns