ADSP-3PARCBF548E02 Analog Devices Inc, ADSP-3PARCBF548E02 Datasheet - Page 69
![KIT DEV STARTER BF548](/photos/9/25/92500/adsp-3parcbf548e02_kit_sml.jpg)
ADSP-3PARCBF548E02
Manufacturer Part Number
ADSP-3PARCBF548E02
Description
KIT DEV STARTER BF548
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
DSPr
Specifications of ADSP-3PARCBF548E02
Contents
Board, Cables, CD, Headset with Microphone, Module, Power Supply
For Use With/related Products
ADSP-BF548
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 69 of 100
- Download datasheet (4Mb)
SD/SDIO Controller Timing
Table 50
Table 51
speed mode) timing.
Table 50. SD/SDIO Controller Timing
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
f
f
t
t
t
t
t
t
t
Spec can be 0 kHz, meaning to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
ISU
IH
PP
OD
WL
WH
TLH
THL
ODLY
ODLY
PP
=1/f
PP
SD_Dx and SD_CMD Input Setup Time
SD_Dx and SD_CMD Input Hold Time
SD_CLK Frequency During Data Transfer Mode
SD_CLK Frequency During Identification Mode
SD_CLK Low Time
SD_CLK High Time
SD_CLK Rise Time
SD_CLK Fall Time
SD_Dx and SD_CMD Output Delay Time During Data Transfer Mode
SD_Dx and SD_CMD Output Delay Time During Identification Mode
OUTPUT
and
and
SD_CLK
INPUT
Figure 43
Figure 44
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
describe SD/SDIO controller timing.
describe SD/SDIO controller (high-
t
THL
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
t
WL
t
PP
t
TLH
t
Rev. C | Page 69 of 100 | February 2010
WH
Figure 43. SD/SDIO Controller Timing
1
t
ODLY
t
ISU
t
IH
Min
7.2
2
0
100
15
15
–1
–1
2
Max
20
400
10
10
14
50
V
V
OL (MAX)
OH (MIN)
Unit
ns
ns
MHz
kHz
ns
ns
ns
ns
ns
ns
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