C8051F411EK Silicon Laboratories Inc, C8051F411EK Datasheet - Page 128

• Manufacturer Part Number: C8051F411EK
• Description: KIT EVAL FOR C8051F411
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F411EK

• Contents: Evaluation Board, CD-ROM, USB Cable, Batteries and User Guide
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F411
• Silicon Family Name: C8051F41x
• Kit Contents: LCD Based Evaluation Board, USB Cable, Software CD And Quick-Start Guide
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• For Use With: 336-1315 - KIT REF DESIGN VOICE RECORD F41X
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1317

C8051F410/1/2/3
15.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
settles above
DD
V
. An additional delay occurs before the device is released from reset; the delay decreases as the V
RST
DD
ramp time increases (V
ramp time is defined as how fast V
ramps from 0 V to V
). Figure 15.2 plots
DD
DD
RST
the power-on and V
monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
DD
delay (T
) is typically less than 0.3 ms.
PORDelay
Note: The maximum V
ramp time is 1 ms; slower ramp times may cause the device to be released from
DD
reset before V
reaches the V
level.
DD
RST
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. The V
monitor is enabled following
DD
a power-on reset.
VDD
V
RS T
1.0
t
/ RST
Logic H IG H
T
P O R D elay
Logic LO W
V D D
P ow er-O n
M onitor
R eset
R eset
Figure 15.2. Power-On and V
Monitor Reset Timing
DD
128
Rev. 1.1