C8051F411EK Silicon Laboratories Inc, C8051F411EK Datasheet - Page 220

• Manufacturer Part Number: C8051F411EK
• Description: KIT EVAL FOR C8051F411
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F411EK

• Contents: Evaluation Board, CD-ROM, USB Cable, Batteries and User Guide
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F411
• Silicon Family Name: C8051F41x
• Kit Contents: LCD Based Evaluation Board, USB Cable, Software CD And Quick-Start Guide
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• For Use With: 336-1315 - KIT REF DESIGN VOICE RECORD F41X
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1317

C8051F410/1/2/3
23.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted into the shift register,
the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive
buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master
device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-buffered,
and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer
will immediately be transferred into the shift register. When the shift register already contains data, the SPI
will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current)
SPI transfer.
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Figure 23.3. 3-Wire Single Master and Slave Mode Connection Diagram
Figure 23.4. 4-Wire Single Master and Slave Mode Connection Diagram
Figure 23.2. Multiple-Master Mode Connection Diagram
Device 1
Master
Master
Device
Master
Device
GPIO
MISO
MOSI
GPIO
MISO
MOSI
MISO
MOSI
NSS
SCK
SCK
SCK
NSS
Rev. 1.1
GPIO
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
NSS
Device 2
Master
Device
Device
Device
Slave
Slave
Slave