C8051F411EK Silicon Laboratories Inc, C8051F411EK Datasheet - Page 202

• Manufacturer Part Number: C8051F411EK
• Description: KIT EVAL FOR C8051F411
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F411EK

• Contents: Evaluation Board, CD-ROM, USB Cable, Batteries and User Guide
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F411
• Silicon Family Name: C8051F41x
• Kit Contents: LCD Based Evaluation Board, USB Cable, Software CD And Quick-Start Guide
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• For Use With: 336-1315 - KIT REF DESIGN VOICE RECORD F41X
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1317

C8051F410/1/2/3
21.5.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the
START condition and transmits the first byte containing the address of the target slave and the data direc-
tion bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the
slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial
data. After each byte is received, ACKRQ is set to ‘1’ and an interrupt is generated. Software must write
the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a ‘1’ to the ACK bit gen-
erates an ACK; writing a ‘0’ generates a NACK). Software should write a ‘0’ to the ACK bit after the last
byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and
a STOP is generated. Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written
while an active Master Receiver. Figure 21.6 shows a typical Master Receiver sequence. Two received
data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’
interrupts occur before the ACK cycle in this mode.
202
Interrupt
S
Figure 21.5. Typical Master Transmitter Sequence
Interrupt
S
Figure 21.6. Typical Master Receiver Sequence
Received by SMBus
Interface
Transmitted by
SMBus Interface
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
SLA
W
R
Interrupt
A
Interrupt
A
Data Byte
Data Byte
Rev. 1.1
Interrupt
Interrupt
A
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Data Byte
Interrupt
Interrupt
A
N
P
P