C8051F411EK Silicon Laboratories Inc, C8051F411EK Datasheet - Page 85
![KIT EVAL FOR C8051F411](/photos/9/25/92547/c8051f411ek_sml.jpg)
C8051F411EK
Manufacturer Part Number
C8051F411EK
Description
KIT EVAL FOR C8051F411
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F411EK
Contents
Evaluation Board, CD-ROM, USB Cable, Batteries and User Guide
Processor To Be Evaluated
C8051F41x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F411
Silicon Family Name
C8051F41x
Kit Contents
LCD Based Evaluation Board, USB Cable, Software CD And Quick-Start Guide
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F41x
For Use With
336-1315 - KIT REF DESIGN VOICE RECORD F41X
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1317
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The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for
n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage) and
the positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN
(shown in SFR Definition 9.1 and SFR Definition 9.6). The amount of negative hysteresis voltage is
determined by the settings of the CPnHYN bits. As shown in Table 9.1, settings of 20, 10 or 5 mV of
negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the
amount of positive hysteresis is determined by setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see
set to logic 1 upon a Comparator falling-edge detect, and the CPnRIF flag is set to logic 1 upon the Com-
parator rising-edge detect. Once set, these bits remain set until cleared by software. The output state of
the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by
setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Compar-
ator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0. When the
Comparator is enabled, the internal oscillator is awakened from SUSPEND mode if the Comparator output
is logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered-on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed. This Power Up Time is specified in Table 9.1 on page 92.
(Programmed with CP0HYP Bits)
Positive Hysteresis Voltage
INPUTS
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis
CP0-
VIN+
CP0+
VIN-
V
Disabled
Figure 9.3. Comparator Hysteresis Plot
OL
V
OH
+
_
CP0
Section “12. Interrupt Handler” on page 110
Positive Hysteresis
Maximum
OUT
Rev. 1.1
Negative Hysteresis
Disabled
Negative Hysteresis
C8051F410/1/2/3
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis Voltage
). The CPnFIF flag is
85
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