MC56F8006DEMO Freescale Semiconductor, MC56F8006DEMO Datasheet - Page 29

DEMO BOARD FOR MC56F8006

MC56F8006DEMO

Manufacturer Part Number
MC56F8006DEMO
Description
DEMO BOARD FOR MC56F8006
Manufacturer
Freescale Semiconductor
Type
DSPr

Specifications of MC56F8006DEMO

Contents
Board
Processor To Be Evaluated
MC56F8006
Interface Type
RS-232, USB
Operating Supply Voltage
3.3 V
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F80xx
Rohs Compliant
Yes
For Use With/related Products
MC56F8006
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
5.3
The 56F8006/56F8002 series contain a dual access memory. It can be accessed from core primary data buses (XAB1; CDBW;
CDBR) and secondary data buses (XAB2; XDB2). Addresses in data memory are selected on the XAB1 and XAB2 buses. Byte,
word, and long data transfers occur on the 32-bit CDBR and CDBW buses. A second 16-bit read operation can be performed
in parallel on the XDB2 bus.
Peripheral registers and on-chip JTAG/EOnCE controller registers are memory-mapped into data memory access. A special
direct address mode is supported for accessing a first 64-location in data memory by using a single word instruction.
The data memory map is shown in
Freescale Semiconductor
1
2
All addresses are 16-bit word addresses.
This RAM is shared with data space starting at address X: 0x00 0000; see
Data Map
Begin/End Address
P: 0x1F FFFF
P: 0x00 83FF
P: 0x00 7FFF
P: 0x00 1FFF
P: 0x00 07FF
P: 0x00 8800
P: 0x00 8000
P: 0x00 2000
P: 0x00 0800
P: 0x00 0000
1
2
All addresses are 16-bit word addresses.
This RAM is shared with Program space starting at P: 0x00 8000. See
Figure
Table 8. Program Memory Map
Begin/End Address
8.
X:0xFF FFFF
X:0xFF FEFF
X:0xFF FF00
X:0x00 FFFF
X:0x00 EFFF
X:0x00 87FF
X:0x00 7FFF
X:0x00 03FF
X:0x01 0000
X:0x00 F000
X:0x00 8800
X:0x00 8000
X:0x00 0400
X:0x00 0000
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
Table
RESERVED
On-Chip RAM
RESERVED
RESERVED
• Internal program flash: 12 KB
• Interrupt vector table locates from 0x00 0800 to 0x00 0865
• COP reset address = 0x00 0802
• Boot location = 0x00 0800
9.
Table 9. Data Memory Map
2
: 2 KB
1
for 56F8002 at Reset (continued)
Memory Allocation
4096 locations allocated
256 locations allocated
Memory Allocation
On-Chip Peripherals
On-Chip Data RAM
RESERVED
RESERVED
RESERVED
RESERVED
EOnCE
1
2 KB
2
Figure
Figure 7
8.
and
Memory Maps
29

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