MC56F8006DEMO Freescale Semiconductor, MC56F8006DEMO Datasheet - Page 5

• Manufacturer Part Number: MC56F8006DEMO
• Description: DEMO BOARD FOR MC56F8006
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8006DEMO

• Contents: Board
• Processor To Be Evaluated: MC56F8006
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8006
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Freescale Semiconductor
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Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging
1.8 V to 3.6 V operation (power supplies and I/O)
From power-on-reset: approximately 1.9 V to 3.6 V
Ambient temperature operating range: –40 °C to 105 °C
Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security and protection that prevent unauthorized users from gaining access to the internal flash
On-chip memory
— 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002
— 2 KB of unified data/program RAM
EEPROM emulation capability using flash
Five interrupt priority levels
— Three user programmable priority levels for each interrupt source: Level 0, 1, 2
— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3
— Lowest-priority software interrupt: level LP
Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine
The masking of interrupt priority level is managed by the 56800E core
One programmable fast interrupt that can be assigned to any interrupt source
Notification to system integration module (SIM) to restart clock out of wait and stop states
Ability to relocate interrupt vector table
One multi-function, six-output pulse width modulator (PWM) module
— Up to 96 MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Phase shifting PWM pulse generation
— Four programmable fault inputs with programmable digital filter
instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace
buffer
Operation Range
Memory
Interrupt Controller
Peripheral Highlights
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
Overview
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