R0K561668S000BE Renesas Electronics America, R0K561668S000BE Datasheet
R0K561668S000BE
Specifications of R0K561668S000BE
Related parts for R0K561668S000BE
R0K561668S000BE Summary of contents
Page 1
To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
Page 2
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
Page 3
H8SX Family 32 Software Manual Renesas 32-Bit CISC Microcomputer H8SX Family The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring ...
Page 4
Rev. 4.00 Sep. 18, 2008 Page ii of xii ...
Page 5
This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
Page 6
Configuration of This Manual This manual comprises the following items: 1. Configuration of This Manual 2. Preface 3. Contents 5. Description of CPU 6. Description of Instructions The configuration of the description of each instruction differs according to the instruction. ...
Page 7
The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward- compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ...
Page 8
Rev. 4.00 Sep. 18, 2008 Page vi of xii ...
Page 9
Section 1 CPU........................................................................................................1 1.1 Features................................................................................................................................. 1 1.2 CPU Operating Modes.......................................................................................................... 3 1.2.1 Normal Mode........................................................................................................ 3 1.2.2 Middle Mode......................................................................................................... 5 1.2.3 Advanced Mode.................................................................................................... 6 1.2.4 Maximum Mode ................................................................................................... 7 1.3 Instruction Fetch ................................................................................................................... 9 1.4 Address Space....................................................................................................................... 9 1.5 Registers ............................................................................................................................. ...
Page 10
Immediate—#xx ................................................................................................. 41 1.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): ................................. 41 1.8.9 Program-Counter Relative with Index Register—@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC)........................................................................ 42 1.8.10 Memory Indirect—@@aa:8 ............................................................................... 42 1.8.11 Extended Memory Indirect—@@vec:7 ............................................................. 43 1.8.12 Effective Address ...
Page 11
BRA BRAnch always ...................................................................... 97 2.2.24 BRA/S BRAnch always with delay Slot ............................................. 99 2.2.25 BRA/BC BRAnch if Bit Cleared.......................................................... 100 2.2.26 BRA/BS BRAnch if Bit Set ................................................................. 102 2.2.27 BSET Bit SET ................................................................................. 104 2.2.28 BSET/EQ Bit SET ...
Page 12
LDMAC 2.2.64 MAC 2.2.65 MOV 2.2.66 MOVA 2.2.67 MOVFPE 2.2.68 MOVMD (B) 2.2.69 MOVMD (W) 2.2.70 MOVMD (L) 2.2.71 MOVSD 2.2.72 MOVTPE 2.2.73 MULS 2.2.74 MULS/U 2.2.75 MULU 2.2.76 MULU/U 2.2.77 MULXS 2.2.78 MULXU 2.2.79 NEG 2.2.80 NOP 2.2.81 ...
Page 13
SLEEP 2.2.104 STC (B) 2.2.105 STC (B) 2.2.106 STC (W) 2.2.107 STC (W) 2.2.108 STC (L) 2.2.109 STM 2.2.110 STMAC 2.2.111 SUB 2.2.112 SUBS 2.2.113 SUBX 2.2.114 TAS 2.2.115 TRAPA 2.2.116 XOR 2.2.117 XORC 2.2.118 XORC 2.3 List of ...
Page 14
Bus Arbitration Timing..................................................................................................... 905 Main Revisions and Additions in this Edition..................................................... 907 Rev. 4.00 Sep. 18, 2008 Page xii of xii ...
Page 15
Section 1 Overview Figure 1.1 CPU Operating Modes .................................................................................................. 3 Figure 1.2 Exception Vector Table (Normal Mode)....................................................................... 4 Figure 1.3 Stack Structure (Normal Mode) .................................................................................... 4 Figure 1.4 Exception Vector Table (Middle and Advanced Modes) .............................................. 6 Figure 1.5 Stack ...
Page 16
Rev. 4.00 Sep. 18, 2008 Page xiv of xxxvi ...
Page 17
Section 1 CPU Table 1.1 Instruction Classification ........................................................................................ 19 Table 1.2 Combinations of Instructions and Addressing Modes (1)....................................... 21 Table 1.2 Combinations of Instructions and Addressing Modes (2)....................................... 24 Table 1.3 Operation Notation ................................................................................................. 25 Table 1.4 Data Transfer Instructions....................................................................................... ...
Page 18
Rev. 4.00 Sep. 18, 2008 Page xvi of xvi ...
Page 19
The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward- compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ...
Page 20
Section 1 CPU • Two base registers Vector base register Short address base register • 4-Gbyte address space Program: 4 Gbytes Data: 4 Gbytes • High-speed operation All frequently-used instructions executed in one or two ...
Page 21
CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. The mode is selected with the mode pins of the LSI or other sources. CPU operating modes 1.2.1 Normal Mode The exception vector ...
Page 22
Section 1 CPU In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the exception vector table is shown in figure 1.2. H'0000 ...
Page 23
Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. • Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program ...
Page 24
Section 1 CPU 1.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas ...
Page 25
Stack Structure The stack structure subroutine branch and that of PC and CCR at an exception handling are shown in figure 1.5. The PC contents are saved or restored in 24-bit units. SP Reserved (a) ...
Page 26
Section 1 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Figure 1.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute ...
Page 27
Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch ...
Page 28
Section 1 CPU 1.5 Registers The H8SX CPU has the internal registers shown in figure 1.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register ...
Page 29
General Registers and Extended Registers 15 ER0 E0 ER1 E1 ER2 E2 ER3 E3 ER4 E4 ER5 E5 ER6 E6 ER7 (SP) E7 Control Registers VBR 31 SBR 63 MAC 31 [Legend] SP: Stack pointer PC: Program ...
Page 30
Section 1 CPU 1.5.1 General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...
Page 31
SP (ER7) 1.5.2 Program Counter (PC 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word multiple of 16 bits, ...
Page 32
Section 1 CPU Initial Bit Bit Name Value 5 H Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R/W Rev. 4.00 Sep. 18, 2008 Page 14 of ...
Page 33
Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC ...
Page 34
Section 1 CPU upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC, and STMAC instructions. 1.5.8 Initial Values of CPU Registers Reset exception handling loads the start address from the vector table into the ...
Page 35
RnH 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH Byte data RnL Word data Rn Word data 15 En MSB 31 Longword data ERn MSB [Legend] ERn: General register ER En: General ...
Page 36
Section 1 CPU 1.6.2 Memory Data Formats Figure 1.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd ...
Page 37
Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 1.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in this manual. Table ...
Page 38
Section 1 CPU Function Instructions Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC 5 Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC [Legend] B: Byte size W: Word size L: Longword ...
Page 39
Table 1.2 Combinations of Instructions and Addressing Modes (1) Classifi- cation Instruction Size Data MOV B/W/L transfer B MOVFPE, B MOVTPE POP, PUSH W/L LDM, STM L 4 MOVA* B/W Block EEPMOV B transfer MOVMD B/W/L MOVSD B Arithmetic ADD, ...
Page 40
Section 1 CPU Classifi- cation Instruction Size Arithmetic MULXS, B/W operations DIVXS MULS, DIVS W/L NEG B W/L EXTU, EXTS W/L TAS B 12 MAC* 12 CLRMAC* 12 LDMAC* 12 STMAC* Logic AND, OR, XOR B ...
Page 41
Classifi- cation Instruction Size Bit BFLD B manipu- BFST B lation Branch BRA/BS BRA/BC* BSR/BS BSR/BC* System LDC B/W* control (CCR, EXR) LDC L (VBR, SBR) STC B/W* (CCR, EXR) STC L (VBR, SBR) ANDC, ORC, ...
Page 42
Section 1 CPU 12. Only when the multiplier is supported Table 1.2 Combinations of Instructions and Addressing Modes (2) Classifi- cation Instruction Size Branch BRA/BS, BRA/BC BSR/BS, BSR/BC Bcc BRA BRA/S JMP BSR ...
Page 43
Table of Instructions Classified by Function Tables 1.4 to 1.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 1.3. Table 1.3 Operation Notation Operation Notation Description Rd General register (destination)* ...
Page 44
Section 1 CPU Table 1.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) MOV B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE B Rs → (EAs) MOVTPE B @SP+ → ...
Page 45
Table 1.5 Block Transfer Instructions Instruction Size Function EEPMOV.B B Transfers a data block. EEPMOV.W Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to ...
Page 46
Section 1 CPU Table 1.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) ADD B/W/L SUB Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data ...
Page 47
Instruction Size Function Rd ÷ Rs → Rd DIVXU B/W Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder bits ÷ 16 bits → 16-bit quotient ...
Page 48
Section 1 CPU Instruction Size Function Rs → MAC LDMAC* — Loads data from a general register to MAC. MAC → Rd STMAC* — Stores data from MAC to a general register. Note: * Only when the multiplier is supported. ...
Page 49
Table 1.8 Shift Operation Instructions Instruction Size Function (EAd) (shift) → (EAd) SHLL B/W/L SHLR Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location ...
Page 50
Section 1 CPU Table 1.9 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified ...
Page 51
Instruction Size Function C ∨ (<bit-No.> of <EAd>) → C BOR B ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The ...
Page 52
Section 1 CPU Instruction Size Function ∼ Z → (<bit-No.> of <EAd>) BISTZ B Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit ...
Page 53
Table 1.11 System Control Instructions Instruction Size Function — TRAPA Starts trap-instruction exception handling. — RTE Returns from an exception-handling routine. — RTE/L Returns from an exception-handling routine, restoring data from the stack to multiple general registers. — SLEEP Causes ...
Page 54
Section 1 CPU 1.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field ...
Page 55
Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 1.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode ...
Page 56
Section 1 CPU 1.8.2 Register Indirect—@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In ...
Page 57
The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, ...
Page 58
Section 1 CPU H'00001001. After execution, ER0 is H'00001002. Example 3: XOR.B R0L, @ER0+ When the value in ER0 before execution is H'00001234, location H'00001234 is read, the read data is EORed with H'35, and the result is written to ...
Page 59
Table 1.13 Absolute Address Access Ranges Absolute Normal Address Mode Data area 8 bits A consecutive 256-byte area (the upper address is set in SBR) (@aa:8) 16 bits H'0000 to (@aa:16) H'FFFF 32 bits (@aa:32) Program area 24 bits (@aa:24) ...
Page 60
Section 1 CPU value should be an even number. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed (H'00). 1.8.9 Program-Counter Relative with Index Register—@(RnL.B, ...
Page 61
Specified by @aa:8 (a) Normal Mode Figure 1.15 Branch Address Specification in Memory Indirect Mode 1.8.11 Extended Memory Indirect—@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the ...
Page 62
Section 1 CPU Table 1.14 Effective Address Calculation for Transfer and Operation Instructions No. Addressing Mode and Instruction Format 1 Immediate op IMM Register direct Register indirect Register indirect with 16-bit displacement ...
Page 63
Table 1.15 Effective Address Calculation for Branch Instructions No. Addressing Mode and Instruction Format Register indirect Program-counter relative with 8-bit displacement 2 op disp Program-counter relative with 16-bit displacement op disp Program-counter relative with index register 3 ...
Page 64
Section 1 CPU Rev. 4.00 Sep. 18, 2008 Page 46 of 914 REJ09B0102-0400 ...
Page 65
Section 2 Instruction Descriptions 2.1 Tables and Symbols This section explains how to read the tables in section 2.2, Instruction Descriptions describing each instruction. Mnemonic Gives the mnemonic of the instruction. [1] Assembly-Language Format Indicates the assembly-language format of the ...
Page 66
Section 2 Instruction Descriptions 2.1.1 Assembly-Language Format Example: ADD. Sz <EAs>, <EAd> Size Mnemonic The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a limited set of operand sizes. The symbol <EA> indicates ...
Page 67
The suffixes :8, :16, :24, and :32 may be omitted. In particular, if the :8, :16, :24, or :32 designation is omitted in an absolute address or displacement, the assembler will optimize the length according to the value range. Note: ...
Page 68
Section 2 Instruction Descriptions Symbol Description ∨ Logical OR ⊕ Logical exclusive OR → Transfer ∼ Logical NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L), ...
Page 69
Register Specification Address Register Specification: When a general register is used as an address register, the register is specified by a 3-bit register field (ers or erd). Data Register Specification: A general register can be used as a 32-bit, ...
Page 70
Section 2 Instruction Descriptions 2.1.6 Bit Data Access in Bit Manipulation Instructions Bit data is accessed as the n-th bit ( … byte data in a general register or the contents of a ...
Page 71
Instruction Descriptions 2.2.1 ADD [1] Assembly-Language Format ADD.Sz <EAs>, <EAd> [2] Operation <EAd> + <EAs> → <EAd> [3] Operand Size Byte, word, longword [4] Description This instruction adds the source operand <EAs> to the contents of the destination location ...
Page 72
Section 2 Instruction Descriptions [6] Available General Registers Usage Source Address register Index register Data register Destination Address register Index register Data register Rev. 4.00 Sep. 18, 2008 Page 54 of 914 REJ09B0102-0400 General Register ER0 to ER7 R0L to ...
Page 73
Available Addressing Modes Source #x:3(1- #x #x: #x: BWL BWL BWL BWL @ERs BWL BWL BWL BWL @(d:2,ERs) BWL BWL BWL BWL @(d:16,ERs) BWL ...
Page 74
Section 2 Instruction Descriptions 2.2.2 ADDS [1] Assembly-Language Format ADDS #1, ERd ADDS #2, ERd ADDS #4, ERd [2] Operation ERd + 1 → ERd ERd + 2 → ERd ERd + 4 → ERd [3] Operand size Longword [4] ...
Page 75
Available Addressing Mode Usage Destination Section 2 Instruction Descriptions Addressing Mode Register direct Rev. 4.00 Sep. 18, 2008 Page 57 of 914 REJ09B0102-0400 ...
Page 76
Section 2 Instruction Descriptions 2.2.3 ADDX [1] Assembly-Language Format ADDX.Sz <EAs>, <EAd> [2] Operation <EAd> + <EAs> → <EAd> [3] Operand Size Byte, word, longword [4] Description This instruction adds the source operand <EAs> and the carry flag ...
Page 77
Available General Registers Usage Source Address register Data register Destination Address register Data register [7] Available Addressing Modes Source #x:3(1-7) #x #x: #x: BWL BWL @ERs BWL BWL @(d:2,ERs) @(d:16,ERs) @(d:32,ERs) @ERs+ ...
Page 78
Section 2 Instruction Descriptions 2.2.4 AND [1] Assembly-Language Format AND.Sz <EAs>, <EAd> [2] Operation <EAd> ∧ (EAs) → <EAd> [3] Operand Size Byte, word, longword [4] Description This instruction ANDs the source operand <EAs> with the contents of the destination ...
Page 79
Available General Registers Usage Source Address register Index register Data register Destination Address register Index register Data register General Register ER0 to ER7 R0L to R7L R7, ER0 to ER7 Byte R0L to R7L, R0H to R7H ...
Page 80
Section 2 Instruction Descriptions [7] Available Addressing Modes Source #x:3(1-7) #x #x: #x: BWL BWL BWL BWL @ERs BWL BWL BWL BWL @(d:2,ERs) BWL BWL BWL BWL ...
Page 81
ANDC [1] Assembly-Language Format ANDC #xx:8, CCR [2] Operation CCR ∧ #IMM → CCR [3] Operand Size Byte [4] Description This instruction ANDs the contents of the condition-code register (CCR) with immediate data and stores the result in CCR. ...
Page 82
Section 2 Instruction Descriptions 2.2.6 ANDC [1] Assembly-Language Format ANDC #xx:8, EXR [2] Operation EXR ∧ #IMM → EXR [3] Operand Size Byte [4] Description This instruction ANDs the contents of the extended control register (EXR) with immediate data and ...
Page 83
BAND [1] Assembly-Language Format BAND #xx:3, <EAd> [2] Operation C ∧ (<bit No.> of <EAd>) → C [3] Operand Size Byte [4] Description This instruction ANDs a specified bit in the destination operand with the carry flag and stores ...
Page 84
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding ...
Page 85
Bcc [1] Assembly-Language Format Bcc disp (cc: Condition field) [2] Operation if condition is true, then PC + disp → PC else next [3] Operand Size [4] Description If the condition specified in the condition field (cc) is ...
Page 86
Section 2 Instruction Descriptions Mnemonic Meaning BPL PLus BMI MInus BGE Greater or Equal BLT Less Than BGT Greater Than BLE Less or Equal Note: If the immediately preceding instruction is a CMP instruction the general register * ...
Page 87
BCLR [1] Assembly-Language Format BCLR #xx:3, <EAd> BCLR Rn, <EAd> [2] Operation 0 → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description This instruction clears a specified bit in the destination operand to 0. The bit number ...
Page 88
Section 2 Instruction Descriptions [6] Available General Registers Usage Bit number specification Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual ...
Page 89
BCLR/EQ [1] Assembly-Language Format BCLR/EQ #xx:3, <EAd> BCLR/EQ Rn, <EAd> [2] Operation if equal (Z = 1), 0 → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description If the specified condition is satisfied, this instruction clears a ...
Page 90
Section 2 Instruction Descriptions [6] Available General Registers Usage Bit number specification Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for ...
Page 91
BCLR/NE [1] Assembly-Language Format BCLR/NE #xx:3, <EAd> BCLR/NE Rn, <EAd> [2] Operation if not equal (Z = 0), 0 → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description If the specified condition is satisfied, this instruction clears ...
Page 92
Section 2 Instruction Descriptions [6] Available General Registers Usage Bit number specification Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for ...
Page 93
BFLD [1] Assembly-Language Format BFLD #xx:8, <EAs>,Rd [2] Operation (<bit field> of <EAs>) → Rd [3] Operand Size Byte [4] Description This instruction loads a specified field in the source operand into an 8-bit register Rd. The specified field ...
Page 94
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Source Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the ...
Page 95
BFST [1] Assembly-Language Format BFST Rs, #xx:8, <EAd> [2] Operation Rs → (<bit field> of <EAd>) [3] Operand Size Byte [4] Description This instruction stores the contents of an 8-bit register (Rs) (data is right-aligned) into a specified field ...
Page 96
Section 2 Instruction Descriptions [6] Available General Registers Usage Source Address register [7] Available Addressing Modes Usage Bit number specification Source Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the ...
Page 97
BIAND [1] Assembly-Language Format BIAND #xx:3, <EAd> [2] Operation C ∧ [∼ (<bit No.> of <EAd>)] → C [3] Operand Size Byte [4] Description This instruction ANDs the inverse of a specified bit in the destination operand with the ...
Page 98
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding ...
Page 99
BILD [1] Assembly-Language Format BILD #xx:3, <EAd> [2] Operation ∼ (<bit No.> of <EAd>) → C [3] Operand Size Byte [4] Description This instruction loads the inverse of a specified bit from the destination operand into the carry flag. ...
Page 100
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding ...
Page 101
BIOR [1] Assembly-Language Format BIOR #xx:3, <EAd> [2] Operation C ∨ [∼ (<bit No.> of <EAd>)] → C [3] Operand Size Byte [4] Description This instruction ORs the inverse of a specified bit in the destination operand with the ...
Page 102
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding ...
Page 103
BIST [1] Assembly-Language Format BIST #xx:3, <EAd> [2] Operation ∼ C → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description This instruction stores the inverse of the carry flag in a specified bit location in the destination ...
Page 104
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding ...
Page 105
BISTZ [1] Assembly-Language Format BISTZ #xx:3, <EAd> [2] Operation ∼ Z → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description This instruction stores the inverse of the zero flag in a specified bit location in the destination ...
Page 106
Section 2 Instruction Descriptions [6] Available General Registers Usage Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding product. ...
Page 107
BIXOR [1] Assembly-Language Format BIXOR #xx:3, <EAd> [2] Operation C ⊕ [∼ (<bit No.> of <EAd>)] → C [3] Operand Size Byte [4] Description This instruction exclusively ORs the inverse of a specified bit in the destination operand with ...
Page 108
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding ...
Page 109
BLD [1] Assembly-Language Format BLD #xx:3, <EAd> [2] Operation (<bit No.> of <EAd>) → C [3] Operand Size Byte [4] Description This instruction loads a specified bit from the destination operand into the carry flag. The bit number is ...
Page 110
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding ...
Page 111
BNOT [1] Assembly-Language Format BNOT #xx:3, <EAd> BNOT Rn, <EAd> [2] Operation ∼ (<bit No.> of <EAd>) → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description This instruction inverts a specified bit in the destination operand. The ...
Page 112
Section 2 Instruction Descriptions [6] Available General Registers Usage Bit number specification Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual ...
Page 113
BOR [1] Assembly-Language Format BOR #xx:3, <EAd> [2] Operation C ∨ (<bit No.> of <EAd>) → C [3] Operand Size Byte [4] Description This instruction ORs a specified bit in the destination operand with the carry flag and stores ...
Page 114
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding ...
Page 115
BRA [1] Assembly-Language Format BRA Rn.Sz Examples: BRA R0L.B BRA R0.W BRA ER0.L [2] Operation → PC [3] Operand Size [4] Description This instruction branches unconditionally to an address which is the result of the ...
Page 116
Section 2 Instruction Descriptions [6] Available General Registers Usage Data register [7] Notes 1. The branch destination address must be even. 2. For details on BRA disp, see section 2.2.8, Bcc Branch conditionally. Rev. 4.00 Sep. 18, 2008 Page 98 ...
Page 117
BRA/S [1] Assembly-Language Format BRA/S disp [2] Operation PC + disp → PC [3] Operand Size [4] Description This instruction branches unconditionally to a specified address after the next instruction (delay slot) is executed. The next instruction should ...
Page 118
Section 2 Instruction Descriptions 2.2.25 BRA/BC [1] Assembly-Language Format BRA/BC #xx:3, <EAs>, disp [2] Operation if bit cleared PC + disp → PC else next [3] Operand Size Byte [4] Description If a specified bit in the source operand is ...
Page 119
Available General Registers Usage Address register [7] Available Addressing Modes Usage Bit number specification Source Section 2 Instruction Descriptions General Register ER0 to ER7 Addressing Mode Immediate Register indirect Absolute address (8 bits) Absolute address (16 bits) Absolute address ...
Page 120
Section 2 Instruction Descriptions 2.2.26 BRA/BS [1] Assembly-Language Format BRA/BS #xx:3, <EAs>, disp [2] Operation if bit set PC + disp → PC else next [3] Operand Size Byte [4] Description If a specified bit in the source operand is ...
Page 121
Available General Registers Usage Address register [7] Available Addressing Modes Usage Bit number specification Source Section 2 Instruction Descriptions General Register ER0 to ER7 Addressing Mode Immediate Register indirect Absolute address (8 bits) Absolute address (16 bits) Absolute address ...
Page 122
Section 2 Instruction Descriptions 2.2.27 BSET [1] Assembly-Language Format BSET #xx:3, <EAd> BSET Rn, <EAd> [2] Operation 1 → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description This instruction sets a specified bit in the destination operand to ...
Page 123
Available General Registers Usage Bit number specification Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding product. ...
Page 124
Section 2 Instruction Descriptions 2.2.28 BSET/EQ [1] Assembly-Language Format BSET/EQ #xx:3, <EAd> BSET/EQ Rn, <EAd> [2] Operation if equal (Z = 1), 1 → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description If the specified condition is satisfied, ...
Page 125
Available General Registers Usage Bit number specification Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding product. Section ...
Page 126
Section 2 Instruction Descriptions 2.2.29 BSET/NE [1] Assembly-Language Format BSET/NE #xx:3, <EAd> BSET/NE Rn, <EAd> [2] Operation if not equal (Z = 0), 1 → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description If the specified condition is ...
Page 127
Available General Registers Usage Bit number specification Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding product. Section ...
Page 128
Section 2 Instruction Descriptions 2.2.30 BSR [1] Assembly-Language Format BSR <EA> Examples: BSR Label BSR R0L.B [2] Operation PC → @−SP Effective address → PC [3] Operand Size [4] Description This instruction pushes the program counter (PC) value onto ...
Page 129
Available General Registers Usage Data register [7] Available Addressing Modes Usage Branch address General Register Byte R0L to R7L Word Longword ER0 to ER7 Addressing Mode Program-counter relative (8-bit displacement) Program-counter relative (16-bit displacement) Program-counter relative ...
Page 130
Section 2 Instruction Descriptions 2.2.31 BSR/BC [1] Assembly-Language Format BSR/BC #xx:3, <EAs>, disp [2] Operation if bit cleared PC → @ disp → PC else next [3] Operand Size Byte [4] Description If a specified bit in the ...
Page 131
Available General Registers Usage Address register [7] Available Addressing Modes Usage Bit number specification Source Section 2 Instruction Descriptions General Register ER0 to ER7 Addressing Mode Immediate Register indirect Absolute address (8 bits) Absolute address (16 bits) Absolute address ...
Page 132
Section 2 Instruction Descriptions 2.2.32 BSR/BS [1] Assembly-Language Format BSR/BS #xx:3, <EAs>, disp [2] Operation if bit set PC → @− disp → PC else next [3] Operand Size Byte [4] Description If a specified bit in the ...
Page 133
Available General Registers Usage Address register [7] Available Addressing Modes Usage Bit number specification Source Section 2 Instruction Descriptions General Register ER0 to ER7 Addressing Mode Immediate Register indirect Absolute address (8 bits) Absolute address (16 bits) Absolute address ...
Page 134
Section 2 Instruction Descriptions 2.2.33 BST [1] Assembly-Language Format BST #xx:3, <EAd> [2] Operation C → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description This instruction stores the carry flag in a specified bit location in the destination ...
Page 135
Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding product. Section 2 Instruction ...
Page 136
Section 2 Instruction Descriptions 2.2.34 BSTZ [1] Assembly-Language Format BSTZ #xx:3, <EAd> [2] Operation Z → (<bit No.> of <EAd>) [3] Operand Size Byte [4] Description This instruction stores the zero flag in a specified bit location in the destination ...
Page 137
Available General Registers Usage Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding product. Section 2 Instruction Descriptions ...
Page 138
Section 2 Instruction Descriptions 2.2.35 BTST [1] Assembly-Language Format BTST #xx:3, <EAd> BTST Rn, <EAd> [2] Operation ∼ (<bit No.> of <EAd>) → Z [3] Operand Size Byte [4] Description This instruction tests a specified bit in the destination operand ...
Page 139
Available General Registers Usage Bit number specification Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding product. ...
Page 140
Section 2 Instruction Descriptions 2.2.36 BXOR [1] Assembly-Language Format BXOR #xx:3, <EAd> [2] Operation C ⊕ (<bit No.> of <EAd>) → C [3] Operand Size Byte [4] Description This instruction exclusively ORs a specified bit in the destination operand with ...
Page 141
Available General Registers Usage Destination Address register [7] Available Addressing Modes Usage Bit number specification Destination [8] Note For details on the accessible ranges for @aa:8 or @aa:16, see the hardware manual for the corresponding product. Section 2 Instruction ...
Page 142
Section 2 Instruction Descriptions 2.2.37 CLRMAC [1] Assembly-Language Format CLRMAC [2] Operation 0 → MACH, MACL [3] Operand Size [4] Description This instruction simultaneously clears registers MACH and MACL available only when the multiplier is supported. [5] ...
Page 143
CMP [1] Assembly-Language Format CMP.Sz <EAs>, EAd [2] Operation <EAd> − <EAs>, set/clear CCR [3] Operand Size Byte, word, longword [4] Description This instruction subtracts the source operand <EAs> from the contents of the destination location <EAd> (destination operand) ...
Page 144
Section 2 Instruction Descriptions [7] Available Addressing Modes Source #x:3(1- #x #x: #x: BWL BWL BWL BWL @ERs BWL BWL BWL BWL @(d:2,ERs) BWL BWL ...
Page 145
DAA [1] Assembly-Language Format DAA Rd [2] Operation Rd (decimal adjust) → Rd [3] Operand Size Byte [4] Description Given that the result of an addition operation performed by an ADD.B or ADDX.B instruction on 4-bit BCD data is ...
Page 146
Section 2 Instruction Descriptions [5] Condition Code — — * — H: Undetermined (no guaranteed value). N: Set the adjusted result is negative; otherwise cleared Set to 1 ...
Page 147
DAS [1] Assembly-Language Format DAS Rd [2] Operation Rd (decimal adjust) → Rd [3] Operand Size Byte [4] Description Given that the result of a subtraction operation performed by a SUB.B, SUBX.B, or NEG.B instruction on 4-bit BCD data ...
Page 148
Section 2 Instruction Descriptions [6] Available General Registers Usage Destination [7] Available Addressing Mode Usage Destination [8] Note Valid results (8-bit register Rd contents, and and H flags) are not assured if this instruction is executed ...
Page 149
DEC (B) [1] Assembly-Language Format DEC.B Rd [2] Operation Rd − 1 → Rd [3] Operand Size Byte [4] Description This instruction subtracts 1 from the contents of an 8-bit register (Rd) (destination operand) and stores the result in ...
Page 150
Section 2 Instruction Descriptions 2.2.42 DEC (W) [1] Assembly-Language Format DEC.W #1, Rd DEC.W #2, Rd [2] Operation Rd − 1 → − 2 → Rd [3] Operand Size Word [4] Description This instruction subtracts the immediate value ...
Page 151
Available Addressing Mode Usage Destination [8] Note An overflow is caused by the operation H'8000 − 1 → H'7FFF, H'8000 − 2 → H'7FFE, or H'8001 − 2 → H'7FFF. Section 2 Instruction Descriptions Addressing Mode Register direct Rev. ...
Page 152
Section 2 Instruction Descriptions 2.2.43 DEC (L) [1] Assembly-Language Format DEC.L #1, ERd DEC.L #2, ERd [2] Operation ERd − 1 → ERd ERd − 2 → ERd [3] Operand Size Longword [4] Description This instruction subtracts the immediate value ...
Page 153
Available Addressing Mode Usage Destination [8] Note An overflow is caused by the operation H'80000000 − 1 → H'7FFFFFFF, H'80000000 − 2 → H'7FFFFFFE, or H'80000001 − 2 → H'7FFFFFFF. Section 2 Instruction Descriptions Addressing Mode Register direct Rev. ...
Page 154
Section 2 Instruction Descriptions 2.2.44 DIVS [1] Assembly-Language Format DIVS.W/L Rs, Rd DIVS.W/L #xx:4, Rd [2] Operation Rd ÷ Rs → ÷ #IMM → Rd [3] Operand Size Word, longword [4] Description This instruction divides the contents of ...
Page 155
Available General Registers Usage Source Destination [7] Available Addressing Modes Usage Source Destination [8] Note The N flag is set to 1 when the signs of the dividend and divisor are different and cleared to 0 when they are ...
Page 156
Section 2 Instruction Descriptions 2.2.45 DIVU [1] Assembly-Language Format DIVU.W/L Rs, Rd DIVU.W/L #xx:4, Rd [2] Operation Rd ÷ Rs → ÷ #IMM → Rd [3] Operand Size Word, longword [4] Description This instruction divides the contents of ...
Page 157
Available Addressing Modes Usage Source Destination [8] Note The N flag is set to 1 when the signs of the dividend and divisor are different and cleared to 0 when they are the same. Accordingly, the N flag will ...
Page 158
Section 2 Instruction Descriptions 2.2.46 DIVXS [1] Assembly-Language Format DIVXS.B/W Rs, Rd DIVXS.B/W #xx:4, Rd [2] Operation Rd ÷ Rs → ÷ #IMM → Rd [3] Operand Size Byte, word [4] Description This instruction divides the lower 16 ...
Page 159
Available General Registers Usage Source Destination [7] Available Addressing Modes Usage Source Destination General Register Byte R0L to R7L, R0H to R7H Word Byte Word ER0 to ...
Page 160
Section 2 Instruction Descriptions 2.2.47 DIVXU [1] Assembly-Language Format DIVXU.B/W Rs, Rd DIVXU.B/W #xx:4, Rd [2] Operation Rd ÷ Rs → ÷ #IMM → Rd [3] Operand Size Byte, word [4] Description This instruction divides the lower 16 ...
Page 161
Available General Registers Usage Source Destination [7] Available Addressing Modes Usage Source Destination General Register Byte R0L to R7L, R0H to R7H Word Byte Word ER0 to ...
Page 162
Section 2 Instruction Descriptions 2.2.48 EEPMOV (B) [1] Assembly-Language Format EEPMOV.B [2] Operation if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L − 1 → R4L Until R4L = 0 else next [3] Operand Size [4] Description This ...
Page 163
EEPMOV (W) [1] Assembly-Language Format EEPMOV.W [2] Operation if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4 − 1 → R4 Until else next [3] Operand Size [4] Description This instruction performs a block ...
Page 164
Section 2 Instruction Descriptions [5] Condition Code — — — — — — H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged. C: ...
Page 165
EXTS [1] Assembly-Language Format EXTS.W/L <EAd> EXTS.L #2, <EAd> [2] Operation Sign extension <EAd> → <EAd> [3] Operand Size Word, longword [4] Description This instruction sign-extends the contents of the destination location <EAd> (destination operand). EXTS.W <EAd> copies the ...
Page 166
Section 2 Instruction Descriptions [5] Condition Code — — — — H: Previous value remains unchanged. N: Set the result is negative; otherwise cleared Set ...
Page 167
EXTU [1] Assembly-Language Format EXTU.W/L <EAd> EXTU.L #2, <EAd> [2] Operation Zero extension <EAd> → <EAd> [3] Operand Size Word, longword [4] Description This instruction zero-extends the contents of the destination location <EAd> (destination operand). EXTU.W <EAd> fills the ...
Page 168
Section 2 Instruction Descriptions C: Previous value remains unchanged. [6] Available General Registers Usage Destination Address register Index register Data register Available Addressing Modes Source Rev. 4.00 Sep. 18, 2008 Page 150 of 914 REJ09B0102-0400 ...
Page 169
INC (B) [1] Assembly-Language Format INC.B Rd [2] Operation → Rd [3] Operand Size Byte [4] Description This instruction increments an 8-bit register (Rd) (destination operand) and stores the result in the 8-bit register (Rd). [5] ...
Page 170
Section 2 Instruction Descriptions [8] Note An overflow is caused by the operation H' → H'80. Rev. 4.00 Sep. 18, 2008 Page 152 of 914 REJ09B0102-0400 ...
Page 171
INC (W) [1] Assembly-Language Format INC.W #1, Rd INC.W #2, Rd [2] Operation → → Rd [3] Operand Size Word [4] Description This instruction adds the immediate value ...
Page 172
Section 2 Instruction Descriptions [7] Available Addressing Mode Usage Destination [8] Note An overflow is caused by the operation H'7FFF + 1 → H'8000, H'7FFF + 2 → H'8001, or H'7FFE + 2 → H'8000. Rev. 4.00 Sep. 18, 2008 ...
Page 173
INC (L) [1] Assembly-Language Format INC.L #1, ERd INC.L #2, ERd [2] Operation ERd + 1 → ERd ERd + 2 → ERd [3] Operand Size Longword [4] Description This instruction adds the immediate value ...
Page 174
Section 2 Instruction Descriptions [7] Available Addressing Mode Usage Destination [8] Note An overflow is caused by the operation H'7FFFFFFF + 1 → H'80000000, H'7FFFFFFF + 2 → H'80000001, or H'7FFFFFFE + 2 → H'80000000. Rev. 4.00 Sep. 18, 2008 ...
Page 175
JMP [1] Assembly-Language Format JMP <EA> Examples: JMP @label:24 JMP @@label:7 [2] Operation Effective address → PC [3] Operand Size [4] Description This instruction branches unconditionally to a specified effective address. [5] Condition Code ...
Page 176
Section 2 Instruction Descriptions [7] Available Addressing Modes Usage Branch address Rev. 4.00 Sep. 18, 2008 Page 158 of 914 REJ09B0102-0400 Addressing Mode Register indirect Absolute address (24 bits) Absolute address (32 bits) Memory indirect Extended memory indirect ...
Page 177
JSR [1] Assembly-Language Format JSR <EA> Examples: JSR @label:32 JSR @@label:8 [2] Operation PC → @−SP Effective address → PC [3] Operand Size [4] Description This instruction pushes the PC value onto the stack as a restart address, ...
Page 178
Section 2 Instruction Descriptions [6] Available General Registers Usage Address register [7] Available Addressing Modes Usage Branch address Rev. 4.00 Sep. 18, 2008 Page 160 of 914 REJ09B0102-0400 General Register ER0 to ER7 Addressing Mode Register indirect Absolute address (24 ...
Page 179
LDC (B) [1] Assembly-Language Format LDC.B <EAs>, CCR [2] Operation <EAs> → CCR [3] Operand Size Byte [4] Description This instruction loads the source operand contents into the condition-code register (CCR). No interrupt requests, including NMI, are accepted immediately ...
Page 180
Section 2 Instruction Descriptions [7] Available Addressing Modes Usage Source Rev. 4.00 Sep. 18, 2008 Page 162 of 914 REJ09B0102-0400 Addressing Mode Register direct 8-bit immediate ...
Page 181
LDC (B) [1] Assembly-Language Format LDC.B <EAs>, EXR [2] Operation <EAs> → EXR [3] Operand Size Byte [4] Description This instruction loads the source operand contents into the extended control register (EXR). No interrupt requests, including NMI, are accepted ...
Page 182
Section 2 Instruction Descriptions [7] Available Addressing Modes Usage Source Rev. 4.00 Sep. 18, 2008 Page 164 of 914 REJ09B0102-0400 Addressing Mode Register direct 8-bit immediate ...
Page 183
LDC (W) [1] Assembly-Language Format LDC.W <EAs>, CCR [2] Operation (EAs) → CCR [3] Operand Size Word [4] Description This instruction loads the source operand contents into the condition-code register (CCR). Although CCR is a byte register, the load ...
Page 184
Section 2 Instruction Descriptions [7] Available Addressing Modes Usage Source Rev. 4.00 Sep. 18, 2008 Page 166 of 914 REJ09B0102-0400 Addressing Mode Register indirect Register indirect with displacement Register indirect with post-increment Absolute address (16 bits) Absolute address (32 bits) ...
Page 185
LDC (W) [1] Assembly-Language Format LDC.W <EAs>, EXR [2] Operation (EAs) → EXR [3] Operand Size Word [4] Description This instruction loads the source operand contents into the extended control register (EXR). Although EXR is a byte register, the ...
Page 186
Section 2 Instruction Descriptions [7] Available Addressing Modes Usage Source Rev. 4.00 Sep. 18, 2008 Page 168 of 914 REJ09B0102-0400 Addressing Mode Register indirect Register indirect with displacement Register indirect with post-increment Absolute address (16 bits) Absolute address (32 bits) ...
Page 187
LDC (L) [1] Assembly-Language Format LDC.L ERs, VBR LDC.L ERs, SBR [2] Operation ERs → VBR ERs → SBR [3] Operand Size Longword [4] Description This instruction transfers the contents of a 32-bit register (ERs) into a base register ...
Page 188
Section 2 Instruction Descriptions 2.2.62 LDM [1] Assembly-Language Format LDM.L @SP+, <register list> [2] Operation @SP+ → ERn (register list) [3] Operand Size Longword [4] Description This instruction restores data saved on the stack to the multiple registers specified in ...
Page 189
Available Addressing Modes Usage Register list [8] Notes 1. If ER7 is selected and saved on the stack, the saved data is read from the stack, however not restored to ER7. 2. The register numbers of ER0 ...
Page 190
Section 2 Instruction Descriptions 2.2.63 LDMAC [1] Assembly-Language Format LDMAC ERs, MAC register [2] Operation ERs → MACH or ERs → MACL [3] Operand Size Longword [4] Description This instruction transfers the contents of a general register to a MAC ...
Page 191
Available Addressing Mode Usage Source [8] Note Execution of this instruction clears the overflow flag in the multiplier to 0. Section 2 Instruction Descriptions Addressing Mode Register direct Rev. 4.00 Sep. 18, 2008 Page 173 of 914 REJ09B0102-0400 ...
Page 192
Section 2 Instruction Descriptions 2.2.64 MAC [1] Assembly-Language Format MAC @ERn+, @ERm+ [2] Operation (EAn) × (EAm) + MAC register → MAC register ERn + 2 → ERn ERm + 2 → ERm [3] Operand Size [4] Description This ...
Page 193
N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged. C: Previous value remains unchanged. [6] Available General Registers Usage Address register [7] Available Addressing Mode Usage General register [8] Notes 1. Flags (N, Z, ...
Page 194
Section 2 Instruction Descriptions • N-MULT (Negative Flag) Saturating mode Setting condition Clearing condition Non-saturating Setting condition mode Clearing condition • Z-MULT (Zero Flag) Saturating mode Setting condition Clearing condition Non-saturating Setting condition mode Clearing condition • V-MULT (Overflow Flag) ...
Page 195
MAC @ER1+,@ER2+ ← Overflow occurs : MAC @ER1+,@ER2+ ← Result = 0 NOP ← CCR ( STMAC MACH,ER3 CLRMAC ← CCR ( STMAC MACH,ER3 ...
Page 196
Section 2 Instruction Descriptions 2.2.65 MOV [1] Assembly-Language Format MOV.Sz <EAs>, <EAd> [2] Operation <EAs> → <EAd> [3] Operand Size Byte, word, longword [4] Description This instruction transfers the source operand <EAs> into the destination location, tests the transferred data, ...
Page 197
Available Addressing Modes Source #x:3(1-7) WL #x:4 #x:8 B BWL BWL BWL #x: #x: BWL BWL BWL BWL @ERs BWL BWL BWL BWL @(d:2,ERs) BWL BWL BWL BWL @(d:16,ERs) BWL ...
Page 198
Section 2 Instruction Descriptions 2.2.66 MOVA [1] Assembly-Language Format MOVA/Sz @(d, <EAs>), ERd [2] Operation d + <EAs> → ERd [3] Operand Size Index: Byte, word [4] Description This instruction zero-extends the source operand (index), shifts the data by the ...
Page 199
Condition Code — — — — — — H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged. C: Previous value remains unchanged. ...
Page 200
Section 2 Instruction Descriptions [8] Notes When the addressing mode of the source operand (index) is register direct and the numbers of the source and destination general registers are the same, the short format can be used. For details, see ...